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through silicon via interconnects

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Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 20-24, November 10–14, 2019,
... scanning electron microscope silicon through-silicon via wavelength-selective absorption Localization of dielectric breakdown sites in 3D through-silicon via (TSV) interconnects by laser stimulation and chip deprocessing K.J.P. Jacobs1, Y. Li1, I. De Wolf1,2, S. Van Huylenbroeck1, E. Beyne1 1 Imec...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 446-453, October 31–November 4, 2021,
...Abstract Abstract This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 109-116, November 14–18, 1999,
... and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 406-413, November 6–10, 2016,
...Abstract Abstract We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 623-630, November 3–7, 2002,
... of the fault is difficult to isolate. RIL (Resistive Interconnect Localization) is a newer technique which can identify via anomalies functionally using induced thermal gradients to the metal but does not address how to uniformly inject the thermal energy required in the silicon to analyze timing design...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 95-102, November 5–9, 2017,
...Abstract Abstract Through Silicon Via (TSV) is the most promising technology for vertical interconnection in novel three-dimensional chip architectures. Reliability and quality assessment necessary for process development and manufacturing require appropriate non-destructive testing techniques...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 1-5, November 15–19, 2020,
...Abstract Abstract With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 163-170, November 14–18, 2010,
... methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 39-43, November 11–15, 2012,
...Abstract Abstract In this paper the new Vion™ Plasma-FIB system, developed by FEI, is evaluated for cross sectioning of Cu filled Through Silicon Via (TSV) interconnects. The aim of the study presented in this paper is to evaluate and optimise different Plasma-FIB (P-FIB) milling strategies...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 7-11, November 3–7, 2013,
... and characterized voids within these interconnections. scanning electron microscope through silicon vias voids X-ray tomography 3D void imaging in Through Silicon Vias by X-ray nanotomography in a SEM David Laloum 1,2 , Pierre Bleuet 2 , Frédéric Lorut 1 , Guillaume Audoit 2 , Celine Ribiere 2 1 ST...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 111-117, November 3–7, 2013,
... 1micron. This indicates that depending on the GDS layout, there exist opportunities to access the metal interconnect layers, even if it has to be done through the transistor. Analyzing FIB Vias and Silicon cuts in Combination While completing the FIB via milling step is challenging, the effect...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 186-190, November 14–18, 2010,
... bonding (which requires real-estate for inter-wafer through- silicon vias connections) allows bonded inter-wafer connections to have minimal consumption of active device area [1]. To understand the metallurgy of the bonding and annealing processes, techniques such as (scanning) transmission electron...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 559-568, November 3–7, 2002,
... the interconnect the actual dimensions of the line, dielectric and vias were determined through precision cross sectioning with a tilt stage FIB * The 4 point method minimizes the probe resistance impact on the measurement. system (Figures 10c, 10d). Data Collection Methodology The outputs of each of the ROC s...
Proceedings Papers

ISTFA1997, ISTFA 1997: Conference Proceedings from the 23rd International Symposium for Testing and Failure Analysis, 211-213, October 27–31, 1997,
... such that the top surface of the device is the backside of the silicon substrate. Pads are not restricted to the periphery of the device so access to the center region of the chip may be required. To access the active device through the bulk silicon a hole must be made in close proximity to the front side active...
Proceedings Papers

ISTFA1996, ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis, 27-35, November 18–22, 1996,
... lines on 0.5 \im silicon. The exposed metal 2 is visible at the bottom of the vias. Fig. 7: cross-section through a minimum FIB via (0.2 um via drill window, 0.2 um width at the base of the via). Note the key hole in the middle of the via (which can be avoided by using appropriate via fill parameters...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 217-224, November 11–15, 2001,
...Abstract Abstract As logic technologies ramp to 0.13 µm and beyond, integrating lower resistance dual damascene copper plated BEOL interconnects with low k (k = 2.65) processing with Dow Chemical’s SiLKTM dielectric and with silicon-on- insulator (SOI) technology offers even higher performance...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 43-50, November 11–15, 2001,
...Abstract Abstract Resistive Interconnection Localization (RIL) is a new scanning laser microscope analysis technique that directly and rapidly localizes defective IC vias, contacts, and conductors from the front side and backside. RIL uses a scanned laser to produce localized thermal gradients...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 317-325, November 14–18, 1999,
... for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines...
Proceedings Papers

ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 461-464, November 15–19, 1998,
... device the easier it will be to implement an edit. The required aspect ratio of a via made with a focused ion beam can double if it must first mill through tens of micrometers of silicon before accessing the diffusion regions. The laser etch process is not typically the limiting factor in producing...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 463-467, November 3–7, 2013,
.... S. Ho, Thermo-mechanical reliability of 3-D ICs containing through silicon vias, in Electronic Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 630 634. [10] M. Sunohara, et al., "Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring," in Electronic...