Surface micromachined micromirror technologies are being employed for various commercial and government applications. One application of micromirror technologies in the commercial sector can be found in Digital Light Projection (DLP™) systems used for theater and home entertainment centers. DLP™ systems developed by Texas Instruments uses DMD™ technology (Digital Mirror Device), an array of micromirrors, to project light onto a screen [1]. This technology is also used by Infocus™ projection systems and widescreen tabletop televisions [2]. Here, the micromirrors act as individual pixels, reflecting light onto the screen with high ¡§digital¡¨ resolution. The most recent application of surface micromachined micromirror technology is optical switching [3], which uses micromirrors to switch optical signals from fiber to fiber for lightwave telecommunications [4]. Companies such as Lucent have fabricated entire optical micromirror switching systems based on their Microstar™ technology [5]. For government applications, surface micromachined micromirror arrays have been developed for potential use in a spectrometer system planned for NASA's Next Generation Space Telescope (NGST) [6]. Various processing technologies are used to fabricate surface micromachined micromirrors. The micromirror arrays developed by TI and Lucent [1,4] uses metal for their structural and reflective components. Micromirrors fabricated at Sandia National Laboratories use the SUMMiT™ (Sandia's Ultra-planar MEMS Multi-level Technology) process with metal deposited on the surface of mechanical polysilicon components to reflect light. Optical micromirror arrays designed and fabricated at Sandia for potential use in the NGST have undergone reliability testing and failure analysis. This paper will discuss the failure modes found in these micromirrors after reliability testing. Suggestions and corrective actions for improvements in device performance will also be discussed.

Listings of the ISTFA 1997 Organizing, Steering, Abstract Review, and Workshop Committees and other contributors.

Listings of the EDFAS 2000-2001 Board of Directors, the ISTFA 2000 Organizing Committee, and other contributors and committee members.

Listings of the ISTFA 1998 Organizing, Steering, Abstract Review, and Workshop Committees and other contributors.

Listings of the EDFAS 1999-2000 Board of Directors, the ISTFA 1999 Organizing and Abstract Review Committees, and other contributors.

Listings of the EDFAS 2001-2002 Board of Directors, the ISTFA 2001 Organizing Committee, and other contributors and committee members.

Listing of the ISTFA 1996 Organizing Committee.

Listings of the EDFAS 2004-2005 Board of Directors, the ISTFA 2004 Organizing Committee Program Chairs, and other contributors and committee members.

In multilevel 3D integrated packaging, three major microstructures are viable due to the application of low volume of solders in different sizes, and/or processing conditions. Thermodynamics and kinetics of binary compounds in Cu/Sn/Cu low volume interconnection is taken into account. We show that current crowding effects can induce a driving force to cause excess vacancies saturate and ultimately cluster in the form of microvoids. A kinetic analysis is performed for electromigration mediated intermetallic growth using multiphase- field approach. Faster growth of intermetallic compounds (IMCs) in anode layer in the expense of shrinkage of cathode IMC layer in shown. This work paves the road for computationally study the ductile failure due to formation of microvoids in low volume solder interconnects in 3DICs.

Listings of the EDFAS 2006-2007 Board of Directors, the ISTFA 2006 Organizing Committee Program Chairs, and other contributors and committee members.

Listings of the EDFAS 2009-2010 Board of Directors, the ISTFA 2009 Organizing Committee and Activities Chairs, and other contributors and committee members.

Listings of the EDFAS 2005-2006 Board of Directors, the ISTFA 2005 Organizing Committee Program Chairs, and other contributors and committee members.

Listings of the ISTFA 2012 User Groups, Moderators, and Presenters.

With the ever decreasing trend in accessibility to hardware tools, the need for software tools is becoming greater than ever for IC fault diagnosis. In this paper, we present a process of studying the limitations and capabilities of fault diagnosis using automated Diagnosis tools, such as FastScan™, as applied to a programmable, parallel processing DSP, The Multimedia Video Processor (TMS320C80). Starting with a brief description of the MVP, we describe how FastScan™ is integrated for supporting fault diagnosis. For establishing the effectiveness of FactScan™ as a diagnostic tool, both the simulation and manufacturing modes of evaluation were done. In simulation mode, both the fault model and the heuristics used by the fault diagnosis software are tested by inserting known defects using a focused ion beam (FIB), machine. This process is then repeated with unknown defects in unknown locations. Experiments on several chips demonstrate the value of the tool and its limitations in relation to detection of classic stuck-at faults and some realistic faults, such as bridging defects.

Listings of the EDFAS 2002-2003 Board of Directors and Committee Chairs, the ISTFA 2002 Organizing Committee, and other contributors and committee members.

Listings of the EDFAS 2008-2009 Board of Directors, the ISTFA 2008 Organizing Committee Program and Activities Chairs, and other contributors and committee members.

Listings of the EDFAS 2003-2004 Board of Directors, the ISTFA 2003 Organizing Committee, and other volunteers and committee members.

Continued technology scaling has led to exposure of many ‘weak-points’ in the designs fabricated in some of the most advanced technology nodes. Weak-points are certain layout patterns which are found to be sensitive to process non-idealities and have a higher tendency to cause defects. They may be coded in the form of Pattern Matching (PM) rules and included within the Design for Manufacturability Guidelines (DFMGs) to ensure product manufacturability. Often, during Integrated Circuit (IC) design, a trade-off is made between meeting performance specifications and complying with DFMGs. As a result, designs may reach the foundry with some DFMG violations. Fixing such violations generally causes a ‘ripple effect’ where one change requires many changes in other metal layers, making the process tedious. Therefore, providing a ranked list of guidelines to the designers helps them in assessing the criticality of violations, prioritizing, and fixing them accordingly. Past research suggests using diagnosis data to determine the impact of DFMG violations. However, this is a reactive approach wherein DFMGs are ranked only based on their hard-defect causing nature. To make the ranking process more robust, we propose a proactive silicon validation based approach which not only considers the yield loss due to hard-defects but also takes into account the parametric and reliability degradation caused by DFMG violations. We evaluate the effectiveness of the proposed methodology through on-silicon experiments on an advanced Fully-Depleted Silicon-On-Insulator (FD-SOI) technology node.

Precise fail site isolation plays a very important role today in the world of semiconductors. Its importance increases more, as the devices are of cutting edge technology with increasing complexity and decreasing dimensions. Global fail site isolations techniques (like XIVA, Photo Emission, FMI etc) and tester based techniques (using automatic test equipment, Fastscan etc) alone, are no longer sufficient and may not be successful. Long net lists and large fail sites isolated by these methods pose problems for physical failure analysis. Planarity of these large areas during parallel lap and inspection times using the SEM is difficult and tedious, thus leading to long cycle times and low resolution rates. There exists a need for precise fail site isolation. In many cases, no single technique can be used to narrow down a fail site significantly. Instead a combination of different techniques must be used. In this paper we present a case study, where a combination of complimentary techniques are used to successfully isolate a fail area of more than 1300 microns in length to less than 100 microns on a single failing net.

Chip access for flip-chip packages in high-performance microprocessors is performed by removing the lid then by extraction of the die from the package substrate. Residual stresses built in temperature cycled (TC) units result in a low success rate using conventional delidding techniques. A need has developed in failure analysis for stress-free removal of the materials surrounding a flip-chip device. This paper discusses a novel, cost effective, wet chemical process that has been developed for thin die and lid removal of flip-chip packaged units. The process uses n-methy-2-pyrrolidone (NMP) for epoxy-based lid attach and underfill materials. A reflux unit is designed to reduce the risk of fire and explosion when the sample is heated in the solvent to the desired temperature. The method of heating reduces the chance of thermal shock, which could fracture the sample due to rapid heating or cooling.