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test margins

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Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 358-364, November 9–13, 2014,
... failure analysis fault location laser-assisted device alteration memory built-in self-test scan chains Marginal Failure Diagnosed with LADA: Case Studies. Sukho Lee, Keonil Kim, Yunwoo Lee, Euncheol Lee, Yojoung Kim Samsung Electronics Co. Ltd., Ki-hung, South Korea sukho.lee@samsung.com Izak...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 410-414, November 10–14, 2019,
...Abstract Abstract Laser Assisted Device Alteration (LADA) or Soft Defect Localization (SDL) is commonly used to root cause device marginality due to functional or structural failures. At a high level, LADA involves setting the device under test (DUT) at its marginal state and using focused near...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 86-98, November 10–14, 2019,
...Abstract Abstract High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 112-117, November 11–15, 2012,
... such as cell stability as well as the static noise margin (SNM). In this work, the cell stability and SNM at different biasing conditions at low electron beam energy (500eV) of a sub-30 nm technology node SRAM device have been characterized. Bit cell stability, static noise margin test as well as leakage study...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 97-102, November 14–18, 1999,
...Abstract Abstract This paper discusses the use of failure analysis techniques, including high-voltage stress testing, to determine the product margin for a microprocessor manufactured on a 0.25-μm CMOS process. The first part of the approach is to define the parametric baseline of the product...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 394-402, October 31–November 4, 2021,
... and implementation are covered in detail and the capabilities of the method, in terms of false fail discovery, elimination, and failure debug, are demonstrated using actual product test cases. ATPG testing genetic algorithms machine learning pin margin analysis test timing optimization yield improvement...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 322-326, November 5–9, 2017,
... an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure. ARM Cortex-A9 atomic force microscopy failure analysis fault isolation fault localization leakage current programmable logic devices scan chains system-on-chip devices...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 377-387, November 14–18, 1999,
... and determining if the defect is marginal. These insights can be helpful for successful failure analysis. application-specific integrated circuits failure analysis Iddq signature analysis test-based analysis 377 Current-Signature-Based Analysis of Complex Test Fails Anne Gattiker IBM Austin Research...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 269-274, November 13–17, 2011,
...Abstract Abstract Owing to the limitations of physical failure analysis (FA) techniques and fault localization techniques, the nano-probing tool, which has both the device characterization ability as well as the necessary sensitivity to characterize the non-visible defects and marginal fails...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 419-422, November 14–18, 2004,
... component helps to screen-out marginal dies and analyze the post-stress spatial pattern. By applying the MERCAD detection system to localize the fault area and the appropriate delayer techniques, metal microbridge is found. In the second case, wafer-sort collects the testing information for the failing scan...
Proceedings Papers

ISTFA1997, ISTFA 1997: Conference Proceedings from the 23rd International Symposium for Testing and Failure Analysis, 31-37, October 27–31, 1997,
... electrical nodes revealed that the leakage occurred through a parasitic field transistor (i.e. between two P+ diffusion islands gated by a polysilicon runner). Probing of test structures with similar layout features revealed that the diffusion isolation between the P+ diffusions was marginal, resulting...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 223-225, November 4–8, 2007,
...Abstract Abstract Non-visual fails have become an ever present complication in the IC industry. Nano probing SRAM bit cells at the inverter level allows the cell to be tested and static noise margin (SNM) to be measured. This paper explains how nano probing of a 65nm technology 6 transistor bit...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 94-96, November 6–10, 2016,
... noise by simulation and proposed calculation of sensing margin change by interference noise. Finally, we expect that a design improvement to reduce the magnitude of interference noise will result in overall improvement when implemented in the test vehicle. capacitive coupling effects data...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 402-406, November 12–16, 2006,
...Abstract Abstract Improving semiconductor yield is a multi-dimensional process that must include design, fabrication, and test aspects. Incorporating design-for-manufacturability (DFM) concepts needs to include prior and ongoing learning and experience on what worked and what did...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 65-69, November 2–6, 2008,
...Abstract Abstract The diagnosis of the failure mode in defective interconnections requires the localization of the failing via before the visualization is performed. The exact localization is challenging when the test array consists of several thousand interconnections and is even more...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 393-395, November 13–17, 2011,
...Abstract Abstract A NOR-type split gate embedded Flash memory product program marginal fail with odd/even word line failure pattern. Based on cell current comparison, programming cycling tests and voltage drop measurements, the invisible cause of even/odd cells weak program failure mechanism...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 526-531, November 11–15, 2012,
... findings serve as useful early data for process improvement feedback. Furthermore, marginal defects, which otherwise are not easily revealed using conventional approach, can also be detected to provide early warning for process drifts or variations. Introduction Scan-based Design for Test (DFT) diagnostics...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 46-48, November 6–10, 2005,
... electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 154-163, November 1–5, 2015,
... machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 366-371, November 10–14, 2019,
...Abstract Abstract Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing...