Convention hand polishing, which is widely used for delayering, is becoming increasingly difficult as metal lines and stacks in semiconductor devices get thinner. For one thing, endpointing at the exact targeted layer and region of interest is a major challenge. The presence of cobalt and its propensity to oxidize, thus complicating electrical measurements, is another challenge. In this study, the authors demonstrate an alternative delayering method based on plasma focused ion beam (PFIB) milling aided by DX gas. The workflow associated with the new method is more efficient than that of conventional hand polishing and can help prevent cobalt oxidation.

This presentation provides an overview of the tools and techniques that can be used to analyze failures in semiconductor devices made with 3D technology. It assesses the current state of 3D technology and identifies common problems, reliability issues, and likely modes of failure. It compares and contrasts all relevant measurement techniques, including X-ray computed tomography, scanning acoustic microscopy (SAM), laser ultrasonics, ultrasonic beam induced resistance change (SOBIRCH), magnetic current imaging, magnetic field imaging, and magneto-optical frequency mapping (MOFM) as well as time domain reflectometry (TDR), electro-optical terahertz pulsed reflectometry (EOTPR), lock-in thermography (LIT), confocal scanning IR laser microscopy, infrared polariscopy, and photon emission microscopy (PEM). It also covers light-induced voltage alteration (LIVA), light-induced capacitance alteration (LICA), lock-in thermal laser stimulation (LI-TLS), and beam-based techniques, including voltage contrast (VC), electron-beam absorbed current (EBAC), FIB/SEM 3D imaging, and scanning TEM imaging (STEM). It covers the basic principles as well as advantages and limitations of each method.

Resolution of optical fault isolation (FI) and nanoprobing tools needs to keep pace with the device downscaling to be effective for semiconductor process development. In this paper we present and discuss state-of-the-art FI and nanoprobing techniques evaluated on Intel test-chips fabricated on next generation process technology. Promising results were obtained but further improvements are necessary for the 7nm node and beyond.

The advances on IC technology have made defect localization extremely challenging. “Soft” failures (resistive vias and contacts) are typically difficult to localize using commonly available failure analysis (FA) techniques such as emission microscopy (EMMI) and scanning optical microscopy (SOM), and often cannot be observed by two-dimensional inspections using layer by layer removal. The article describes the Resistive Contrast Imaging (RCI) defect localization technique (also known as Electron Beam Absorbed Current (EBAC), instrumentations, and case studies on test structures or process control monitors especially designed to detect “soft” open failures on advanced (28nm and below) technology devices. It also lists the key SEM parameters critical for effective FA using the RCI nano-probing system.

This paper presents a method of using a conductive atomic force microscope (C-AFM) to characterize a submicron metal fuse that has been blown open inadequately by laser. In order to obtain a proper I-V curve measured using the C-AFM without affecting the incompletely opened fuse, the paper proposes a method of preserving the fuse by coating its surface with spin-on glass. The paper explains how differences in laser cutting machines resulted in the high failure repair rate of customer product despite equivalent energy and spot size settings. Analysis of the fuse bank circuitry on wafers helped to find the critical physical differences between a fully blown and a poorly blown fuse. By overcoming difficulties in preserving the blown fuse failure sites for C-AFM measurement, laser settings could be easily optimized to ensure proper fuse opening.

This article presents a novel method to provide whole Deep Trench (DT) profile inspection. Bevel angle top-down polishing is used on pre-rotated substrates instead of traditional cross-section cleaving. This method can feedback the precise DT profile shape at specific depths to the production line for process tuning and troubleshooting.

Optical beam induced resistance change (OBIRCH) is one popular technique for isolating electrical shorts in process development test structures for 130nm and 110nm device technologies. However, OBIRCH inspection on 90nm technology is not always successful: since the OBIRCH signals of samples are very weak, or even comparable to noise. To overcome this, two alternative and complementary methods for isolating the failure have been developed. The first method is to calculate the coarse position of the defect directly from electrical resistance measurements. The second method is to enhance the OBIRCH signal using FIB circuit modification within the test structure. These methods can help locate defect at this structure by using electrical analysis only or enhancing the OBIRCH signal. The first method is an easy and quick method for short failure isolation, while the second can exactly locate the position of failure if the first method does not reveal a surface defect.

Multi-Chip Package (MCP) decapsulation is now becoming a rising problem. Because for traditional decapsulation method, acid can’t dissolve the top silicon die to expose the bottom die surface in MCP. It makes inspecting the bottom die in MCP is difficult. In this paper, a new MCP decapsulation technology combining mechanical polishing with chemical etching is introduced. This new technology can remove the top die quickly without damaging the bottom die using KOH and Tetra-Methyl Ammonium Hydroxide (TMAH). The technology process and relative application are presented. The factors that affect the KOH and TMAH etch rate are studied. The usage difference between the two etchant is discussed.

This article describes a 90nm technology SRAM soft fail analysis. The bitmaps of affected wafers show a large number of wafer edge dies failing with single cell cluster fails at supply voltages below 1.0V. The fails appear in characteristic areas within a 256k dualport SRAM memory block. Nanoprobing was used for electrical localization at the cell level by means of a Multiprobe atomic force probe (AFP) system. Fail areas exhibit very weak PFET drain currents several orders of magnitude below the target values, while the drain currents of NFET cell transistors are in the expected range. For fail visualization a junction stain was applied to TEM samples to delineate areas with different doping levels. Due to differences in etch behavior between failed and reference areas, missing LDD extensions and a partially blocked source/drain (S/D) implantation were identified as the root cause of the fails.

Ultra low voltage probing by time resolved emission (TRE) technology below 1.0V is very challenging for micro-processor debug in practical operation condition. This is because the photo-emission rate reduces exponentially as the power supply voltage decreases. In this paper, a novel technology with improved detector in solid immersion lens (SIL) TRE system was demonstrated for low voltage and small node probing. An improved detecting scheme was developed to collect 30% more photon detection efficiency than the previous system. The SIL TRE with low dark noise detector technology has been successfully applied to optical probing for 45nm product debug. The performance gain improvement in strong and weak signal regime has been demonstrated against the current detector technology. It has also demonstrated the capability on probing the ultra low voltage at 0.75 V for sub micron node of 45nm process.

The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

In many cases it is difficult to distinguish mechanical damage from electrostatic surface impacts. In recent years, several investigations have resulted in publications on ESDFOS (Electrostatic Discharge From Outside to Surface). While the diagnostics of the phenomena have been worked out quite well for wafers with aluminum metallization, no formal studies on ESDFOS impact to copper-metallized wafers have been published. This paper investigates physical features of Cu-metallized wafers artificially exposed to ESDFOS impacts of variable severity, producing an understanding of damage features to more easily facilitate recognition of EDSFOS events.

A methodology for detecting silicide pipes on SOI technology in-line soon after their formation is described. Techniques currently exist to detect pipes in-line, but only much later in the process. This methodology, which is based on voltage contrast inspection of test structures, allows experiments to be completed more quickly providing much faster cycles of learning. Two different test structures are described. The first one was designed for other purposes but was adopted for silicide pipe detection at M1. The second was specially designed and allows pipe detection at silicide anneal, W CMP and M1. A procedure for determining the cause of buried shorts detected by the eS32 is also described. Experimental results are presented to demonstrate the benefit of this technique.

It has been found that a process-design interaction involving very large capacitor arrays is capable of causing voiding in well-formed copper trenches. This voiding is believed to be caused by the electrochemical dissolution of copper driven by the photovoltaic effect realized at p-n junctions. A series of experiments was performed to reproduce this voiding in a laboratory environment using water and exposure to light or dark. The experiments were performed on two different size capacitor arrays. In addition, similar experiments were performed on a large capacitor array that uses the opposite dopant isolation scheme. Conversely, copper dendrite growth was observed at the features of interest instead of dissolution, even under flowing de-ionized water (DI) conditions. The results are discussed in the context of known copper-water electrochemical equilibria and design implications are discussed.

We present the results of recent failure analysis of an advanced, 0.5 um, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

Laser microchemical (LMC) technology has become an important element of the FIA and debug tool set by supplying key steps not well addressed by previous tools. In this paper we report the optimization of the LMC technology to solve key issues for flip chip FIA. Specific processes have been developed for localized thinning of flip chips, in order to enable access of conventional FIA tools. Additional applications include dramatic enhancement of focused ion beam (FIB) rework and 3-D micromachining for prototyping, in-situ trimming, and mastering of microelectromechanical systems (MEMS). Laser etching of silicon is with a high pressure chlorine assist and is l000X the rate of the fastest focused ion beam methods. In contrast to grinding methods, the process introduces no process stress or contamination and retains an average surface roughness of several hundred angstroms. Micronthickness metal lines are laid down in a one-step vapor phase deposition at 200 μm/s writing speed. Rapid deposition combined with the superior quality of the laser interconnect, translates into writing with a conductance per unit writing time of 1000 to 10,000 times the rate of a focused ion beam.

Focused Ion Beam (FIB) has been widely accepted in circuit modification and debugging of new chips and process technologies [1]. It has the advantages of rapid confirmation of design fixes and reducing the cost and time to build new masks. In this paper, we will describe the latest application of FIB to debugging Static Random Access Memory (SRAM) test chips processed on a dense copper metallization technology. Examples of finding leaky capacitors will be given. Individual transistors in the cell array have also been “fibbed” and characterization curves were measured. We compare the measurement with the SPICE simulation and discuss possible damage to the underlying transistors during FIB pad creation. Resistors in the periphery circuit were fibbed and measured with two and four point probes. Contact resistance was characterized and compared to that of Al interconnects. Example of finding problem vias with the help of cross-section and voltage contrast is given.

Smaller technologies and increasing chip functionality has resulted in tightly packed devices and more stacked metal layers. For technologies between 0.25µm and 0.14 µm, stacking packed metal layers required the combination of Tungsten plugs as interconnection and the utilization of Chemical Mechanical Polishing (CMP). “Pillar”, however, is a small metal line, which allows interlevel connections between Tungsten plugs. The size and shape of the pillar can be a yield limiting issue. The process of identification and resolution of the missing metal pillar included yield analysis, electrical and physical failure analysis, root cause analysis and the engineering coordination of photo engineering, etch process engineering, CMP engineering, integration engineering, and inline inspection. Resolving the missing pillar issue has proven to have significant contribution to yield.

The limitation of Focused Ion Beam (FIB) and all charged beam technologies are their insensitivity to the internal composition of materials relative to surface composition. For the most part, charged particle technology cannot provide the resolution at a depth necessary for locating traces either buried under passivation or through silicon. Before CMP planarization was utilized in the industry, it was possible to correlate passivation topography with buried metal traces and manually navigate to the correct x-y coordinates necessary for edit placement. There was still a level of difficulty and CAD navigation helped immensely. With the advent of CMP-planarized metallization, CAD navigation became a necessity, yet still required passivation topography for precise alignment. Current manufacturing processes now planarize all layers, including the passivation, increasing the overall difficulty of navigation. Techniques of drilling “seeker” holes or surface demarcation using FIB and lasers to establish reference fiducials are used extensively [1,2]. Seeker holes and optical-to-FIB image correlation have been useful workarounds for the navigation-related problems presented by advanced ICs. In this paper we will discuss the advantages of Real-Time Optical Imaging coaxially integrated into the FIB, providing non-invasive navigation to nodes for front side and backside applications.

In this paper we examine the use of the Superconducting Single-Photon Detector (SSPD) [1] for extracting electrical waveforms on an IBM microprocessor fabricated in a 0.13µm technology with 1.2V nominal supply voltage. Although the detector used in our experiments is prototype version of the one discussed in [1] demonstrating lower performance, we will show that it provides a significant reduction in acquisition time for the collection of optical waveforms, thus maintaining the usability of the PICA technique for present and future low voltage technologies.