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Root cause failure analysis of lithium-ion batteries provides important feedback for cell design, manufacture, and use. As batteries are being produced with larger form factors and higher energy densities, failure analysis techniques must be adapted to characteristics of the specific batteries. This paper will discuss the significance of melted copper in lithium-ion battery cells that have experienced thermal runaway and how the interpretation of such evidence has evolved over time. Specialized testing techniques that may prove helpful in determining the root cause of battery failures will also be described.

This paper reports the novel application of Plasma Focused Ion Beam (pFIB) to reveal subtle defects in advanced technology nodes. Two case studies presented, both of which alter the standard work procedure in order to find the defects. The first case highlights the precise milling capability of pFIB in discovering the metal buried via void that is easy-to-miss by standard failure analysis (FA) practice. The second utilizes pFIB circuit edit process to facilitate electrical isolation in pinpointing the exact failure location and thus enables identifying the defect more efficiently.

We present the results of recent failure analysis of an advanced, 0.5 um, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

Within this paper, the authors present an adapted FA flow for state-of-the-art Package Failure Analysis for 20nm technology and below. As a key aspect, three methods (EOTPR, 3D Xray & PFIB) are introduced as the next-gen FA standard methods for emerging package technologies such as TSV, u-pillar bumping and stacked-die devices. By showing different types of daily Package FA requests, the paper compares & discusses important factors such as turn-around-time (TAT), success yield and results quality. In the end, an outlook is given how recent developments on these techniques will help to establish a new standard FA flow.

The increase in complexity of process, structure, and design not only increases the amount of failure analysis (FA) work significantly, but also leads to more complicated failure modes. To meet the need of high success rate and fast throughput FA operation at the leading-edge nodes, novel FA techniques have to be explored and incorporated into the routine FA flow. One of the novel techniques incorporated into the presented scan logic FA flow is the conductive-atomic force microscopy (CAFM) technique. This paper demonstrates CAFM technique as a powerful and efficient solution for scan logic failure analysis at advanced technology nodes. Several failure modes in scan logic FA are used as examples to illustrate how CAFM provides excellent solutions to some of the very challenging FA problems. The gate to active short in nFET devices, resistive contact, and open defect on gate contact are some modes used.

Laser microchemical (LMC) technology has become an important element of the FIA and debug tool set by supplying key steps not well addressed by previous tools. In this paper we report the optimization of the LMC technology to solve key issues for flip chip FIA. Specific processes have been developed for localized thinning of flip chips, in order to enable access of conventional FIA tools. Additional applications include dramatic enhancement of focused ion beam (FIB) rework and 3-D micromachining for prototyping, in-situ trimming, and mastering of microelectromechanical systems (MEMS). Laser etching of silicon is with a high pressure chlorine assist and is l000X the rate of the fastest focused ion beam methods. In contrast to grinding methods, the process introduces no process stress or contamination and retains an average surface roughness of several hundred angstroms. Micronthickness metal lines are laid down in a one-step vapor phase deposition at 200 μm/s writing speed. Rapid deposition combined with the superior quality of the laser interconnect, translates into writing with a conductance per unit writing time of 1000 to 10,000 times the rate of a focused ion beam.

Three case studies in which the passive voltage contrast technique (PVC) was used in-fab during the development of a 0.25μm ASIC CMOS technology for rapid characterization and failure isolation are presented. The first case involved using the PVC technique to evaluate the gate oxide quality at different points of the process, allowing for quick identification of the process steps that were damaging the gate oxide and the relative magnitude of the damage that each process step contributed. PVC was then used to perform in-line evaluation of the split lots that were ran to address the problem without having to pull wafers off the line for electrical testing. In the second case study, PVC was used in-line to identify the source of siliciderelated gate-to-source/drain leakage. At this point of the process, electrical probing was not possible, and PVC circumvented this problem. The third case involved using PVC to help identify a new failure mechanism for tungsten plug vias that manifested itself due to plasma charging and layout peculiarities related to deep submicron design rules.

An investigation into a high resistance via problem during the development phase of an advanced 0.25µm CMOS ASIC process is presented. The electrical signature of the via problem was low yield on fully processed device wafers. Further testing revealed that the logic (cell-based) sections of the chip were functioning, however the 512K bit SRAM was consistently failing. Based on the failing bit pattern, the failure area was isolated to contact-via stacks in the cell. Advanced wafer level failure analysis techniques and equipment such as focused ion beam milling, precision cross-section, and planar polishing techniques were utilized to identify the layer that was failing. Analysis results indicated a thin foreign layer or void between the aluminum line and the cap barrier layer of the line. Placement of a via on this line resulted in a high resistance node and subsequent device failure. As a further verification of the electrical failing signature, SPICE simulation was run on the SRAM cell circuitry. Optimization of the metallization stack was performed through experiments which resulted in the elimination of the mechanism.

Flip Chip packaging requires an understanding of the solder bump metallurgy and its aging characteristics. In this paper we demonstrate how standard failure analysis techniques can help determine aging characteristics and, how an understanding of bump age can be successfully employed to enhance bump reliability.

Dual beam FIBSEM systems invite the use of innovative techniques to localize IC fails both electrically and physically. For electrical localization, we present a quick and reliable in-situ FIBSEM technique to deposit probe pads with very low parasitic leakage (Ipara < 4E-11A at 3V). The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance. The buried plate (n-Band), p-well, wordline and bitline of a failing and a good 0.2 μm technology DRAM single cell were contacted. Both cells shared the same wordline for direct comparison of cell characteristics. Through this technique we electrically isolated the fail to a single cell by detecting leakage between the polysilicon wordline gate and the cell diffusion. For physical localization, we present a completely in-situ FIBSEM technique that combines ion milling, XeF2 staining and SEM imaging. With this technique, the electrically isolated fail was found to be a hole in the gate oxide at the bad cell.

During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (I DDQ ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable I DDQ that fluctuated rapidly. We refer to this condition as “jitter.” The I DDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island.

A novel optical probing technique to measure voltage waveforms from flip-chip packaged complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) is described. This infrared (IR) laser based technique allows signal waveform acquisition and high frequency timing measurement directly from active PN junctions through the silicon backside substrate on IC’s mounted in flip-chip, stand-alone, or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug & failure analysis (FA) through-put time (TPT) as compared to backside electron-beam (E-beam) probing because of the elimination of backside trenching and probe hole generation operations.

With further miniaturization of MOS devices, the thickness of gate oxides becomes thinner and thus more sensitive to damage. Emission microscopy has shown its capability in analysis of these failures. However, emission site is not always the exact location of the physical defect. High-density devices with multi-metal layers make the situation worse. But when it is combined with Passive Voltage Contrast (PVC) technique, the success rate of isolating such failures can be greatly increased. In a case study, a unit of 1M bits Static Random Access Memory (SRAM), fabricated by 0.25 µm technology with 5 metal layers, failed after 500 hours burn-in. We successfully isolated the leaky poly and subsequently found gate oxide pinholes with the combination of PVC technique and emission analysis.

Focused ion beam (FIB) techniques are continuously improved to meet the demands of shrinking device dimensions and new technologies. We developed a simultaneous milling and deposition FIB technique to provide electrical contact to small buried targets in semiconductors. This method is applied to directly connect the deep trench (DT) capacitor of a DRAM single cell in deep submicron technology. By carefully adjusting the deposition parameters (scanned area < (0.3 µm)2, beam current < 20 pA) we are able to influence diameter, depth and Pt fill properties of the hole to meet the very restricted requirements for successful DT connection (hole diameter < 200 nm at DT level). Electrical measurements are performed on DRAM single cells after connecting buried plate (n-band), p-well, wordline, bitline and DT. The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance by using a dualbeam FIB. The read and write conditions of an active memory cell are studied. The presented method increases the capabilities to localize and characterize trench related failure mechanisms.

A new Au etch, recently developed for selective Au etching on Ti/Pt/Au metallization of optoelectronic devices, has been tested on Au wires bonded on Al films. Contrary to theoretical expectations, Au wires are removed without Al damage, except for a very localized area around the bond interface. The role of the native Al oxide is discussed in preserving Al and allowing Au lift off.

This paper discusses the challenges involved in testing microprocessors incorporating silicon-on-insulator (SOI) technology and assesses new characterizations tools, such as scanning capacitance microscopy (SCM), focused ion beam (FIB) analysis, and AFM electrical probing, that show promise when used to examine SOI device anomalies and failure modes.

The work presented in this paper concerns the characterization of MEMS structures, industrially manufactured using front-side bulk micromachining post-process techniques on CMOS dies. The systematic characterization of mechanical parameters, such as stiffness or mass, on a set of 100 cantilever devices provide us with basic knowledge concerning process parameter variations.

Infrared Micro Thermography can be applied as electrical fault identification in situations where photon emission is ineffective. Defects, such as certain types of stringers and particles, may conduct without emitting photons in the visible range. Arrayed infrared sensors such as an InSb 512x512 detector, coupled with the appropriate infrared optics can image the heat generated from the leakage site. Heating on the order of a fraction of a degree Kelvin can be observed. The heat signature can be superimposed on a normal optical image of the chip. Several practical examples using this fault identification technique are described.

Focused Ion Beam (FIB) has been widely accepted in circuit modification and debugging of new chips and process technologies [1]. It has the advantages of rapid confirmation of design fixes and reducing the cost and time to build new masks. In this paper, we will describe the latest application of FIB to debugging Static Random Access Memory (SRAM) test chips processed on a dense copper metallization technology. Examples of finding leaky capacitors will be given. Individual transistors in the cell array have also been “fibbed” and characterization curves were measured. We compare the measurement with the SPICE simulation and discuss possible damage to the underlying transistors during FIB pad creation. Resistors in the periphery circuit were fibbed and measured with two and four point probes. Contact resistance was characterized and compared to that of Al interconnects. Example of finding problem vias with the help of cross-section and voltage contrast is given.