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system-on-chips

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Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 161-168, October 28–November 1, 2018,
... that the customer may be diagnosing their system in a fashion that may not be necessarily the same as the one used in the FA laboratory. Such mismatches cause miscorrelation between the customer failure mode and the analyst s observation. Hence, the customer and the FA may enter an endless cycle of arguing whether...
Proceedings Papers

ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 193-197, November 15–19, 2009,
...Abstract Abstract Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 439-442, November 13–17, 2011,
...Abstract Abstract Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 436-445, November 9–13, 2014,
... be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 322-326, November 5–9, 2017,
...Abstract Abstract Failure analysis and defect localization on 28nm All Programmable Zynq System-on-Chip (SoC) device is extremely challenging. While conventional FPGA, which only consists of the Programmable Logic, has greater ease and flexibility in pattern generation during fault isolation...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 176-182, October 28–November 1, 2018,
...Abstract Abstract Bitmapping based on memory built-in self-test is the most efficient method to locate embedded memory defects in system-on-chips. Although this is the preferred approach to memory yield improvement, the procedure to enable bitmapping can be both time and resource-consuming...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 184-190, November 5–9, 2017,
...Abstract Abstract Most modern system on-chip incorporates a significant amount of embedded memories to achieve a reduced power consumption, higher speed and lower cost. In general, such memories are evaluated using built-in self-testing methods and in the event of a failure, bitmapping...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 553-557, November 3–7, 2002,
... (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling. chemical vapor deposition current density dielectrics...
Proceedings Papers

ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 329-333, November 15–19, 2009,
...Abstract Abstract A system-on-chip processor (90 nm technology node) was experiencing a high basic function failure rate. Using a lab-based production tester, laser assisted device alteration, nanoprobing, and physical inspection; the cause of failure was traced to a single faulty P channel...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 482-485, November 3–7, 2013,
... a higher success rate at subsequent physical failure analysis of complex modern RF System on a Chip. automatic test pattern generation failure analysis mobile applications radio frequency communication system on chips...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 336-340, November 3–7, 2013,
... of these challenges over the past two decades, and ongoing development of advanced detectors and optical systems continue and are essential to continued progress.[1-3] Additional challenges are presented when one wishes to test and characterize the diagnostic tools themselves. Differences in circuit design styles...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 617-622, November 3–7, 2002,
... interconnect testing is possible but all TBM s must be synchronized or one board within the backplane configuration must become the Master. Figure 8: Passive Backplane Local Test Bus Master Passive Backplane System Test Bus Master In this configuration one module in the backplane is the system Master...
Proceedings Papers

ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 455-459, November 15–19, 1998,
...Abstract Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 12-18, November 9–13, 2014,
... the same conditions reliably, in conjunction with small variations in Silicon substrate thickness and surface preparation quality, the best focal Z position may change from one position to the next, along the raster scanning path. Thanks to the large number of SIL images acquired using our proposed system...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 285-288, November 11–15, 2001,
... tool in debug and analysis of semiconductor chips. With the introduction of copper, many of the current FIB chemistries and techniques will need to be modified in order to accommodate this process. The metal etch gases currently in most FIB systems either have no effect on copper or have detrimental...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 141-146, November 1–5, 2015,
... isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete...
Proceedings Papers

ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 503-507, November 12–16, 2000,
.... Magnetic-Field Imaging System One way to overcome some of these difficulties is a new technique that enables magnetic-field imaging. From magnetic-field images, the source currents can be calculated providing the failure analyst the ability to see a map of current in the device. By mapping the current...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 14-20, November 6–10, 2005,
...Abstract Abstract The scanning laser-SQUID microscope can detect electrical defects in a chip without requiring electrical contacts to the chip. Using our new system, we can get magnetic flux images of a 300mmɸ wafer in air. Experiments with 256Mbit-DRAM chips showed that IDDS testing results...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 269-273, October 31–November 4, 2021,
... removal technique, particularly for fin field-effect transistors (FinFETs). Here, success depends on certain factors, one of which is the location of the AOI. If the AOI is near the edge of the chip, finger deprocessing can be very difficult because material removal rates are much higher there than...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 471-476, November 14–18, 1999,
... to navigate and locate emission sites. The detector has high quantum efficiency (QE) well beyond 1.1 micron (Fig. 1). This feature allows detection of not only hot carrier emission but also black body radiation even at room temperature. The system is equipped with two sets of optics. One set of warm (TA...