Boundary-scan is a technology that’s been around for over ten years and is delivering the results foreseen by the IEEE working group that developed the 1149.1 specification. Many SMT (surface mount) production lines around the world use boundary-scan to solve the testing challenges presented by today’s complex designs. These users are realizing the vision of the specification, using it to restore test access and fault coverage to assemblies with few physical test points relative to the number of electrical nets to be tested. As the boundary-scan standard has gained acceptance and credibility, users, chip vendors and tools providers have developed important extensions of the original vision. Among the extensions already available or under active consideration is the use of boundary-scan for analog testing, concurrent programming of multi-vendor cPLD’s, dynamic verification of high-speed communication channels, and application within higher-level electronic assemblies beyond printed circuit boards i.e. to subsystems and systems. This paper describes the effectiveness of boundaryscan at the system level, focusing on the use of IEEE Std. 1149.1 compatible devices and ATPG tools to accomplish system level testing and in-system configuration.

Completion of failure analysis (FA) cases require a lot of expensive equipment and tools. Equipment Management System (EMS) is a must to safeguard the equipment from being down/damaged due to uncertified/untrained and high number of users and to avoid high repair cost of the FA laboratory equipment. The purpose of this paper is to present the RFID-based equipment management system for failure analysis laboratory equipment which has the capability to limit the equipment usage to authorized and certified users, locks and unlocks the equipment, and controls the real-time status of the equipment.

Counterfeit integrated circuits (ICs) continue to persist in the supply chain causing early failure in electronics that unknowingly incorporate them. With counterfeiters becoming more adept at replicating ICs, the need for systems and processes to identify counterfeit ICs has been growing in recent years. In this paper, we benchmark the resonant cavity system (ResCav) by evaluating its ability to distinguish ICs with minor circuit variations. A baseline IC group along with 5 variant groups with changes made solely to their die were examined in this paper. Using a supervised machine learning algorithm, the system was able to distinguish every group of ICs amongst each other with an average weighted precision above 90% in every comparison scenario. The system’s ability to distinguish these subtle changes means that it would be suitable when used as a system for counterfeit detection, where the detection of minor deviations is pertinent. This could ultimately lead to the creation of a rapid, precise, and non-destructive system that can screen ICs for conformance.

With the introduction of flip-chip technology, optical-based failure analysis techniques have played a critical role in many failure analysis (FA) laboratories. This is due to the unhindered access for photons to probe or emit from the transistor layer through the bulk silicon. Among the optical techniques, laser voltage imaging (LVI) and laser voltage probing (LVP), collectively called LVx, dominate because they directly expose the electrical activity of a given circuit or cell.

An approach to overcome barriers to practical Compressed Sensing (CS) implementation in serial scanning electron microscopes (SEM) or scanning transmission electron microscopes (STEM) is presented which integrates scan generator hardware specifically developed for CS, a novel and generalized CS sparse sampling strategy, and an ultra-fast reconstruction method, to form a complete CS system for 2D or 3D scanning probe microscopy. The system is capable of producing a wide variety of highly random sparse sampling scan patterns with any fractional degree of sparsity from 0- 99.9% while not requiring fast beam blanking. Reconstructing a 2kx2k or 4kx4k image requires ~150-300ms. The ultra-fast reconstruction means it is possible to view a dynamic reduced raster reconstructed image based upon a fractional real-time dose. This CS platform provides a framework to explore a rich environment of use cases in CS electron microscopy that benefit from the combination of faster acquisition and reduced probe interaction.

Certain device failures are especially difficult to analyze since they can only be reproduced under high speed and high power conditions, while also requiring the removal of standard heat dissipating packaging to get visual access to the chip. In addition to the challenge of heat generation density of devices increasing year by year, small hot spots in actual usage generate heat far in excess of the average, and heat dissipation performance needs to be more efficient and highly uniform. In addition, it is desirable to implement a cooling system that does not overly restrict the number and types of lenses that can be used, such as high and low magnification air gap lenses as well as a solid-immersion lens, which has been one of the challenges of existing systems. This paper reports on the development of a cooling system to address these challenges and to enable failure analysis on a device running at 200 W.

The Fluorescent Microthermal Imaging (FMI) technique was developed as a new failure analysis tool for hot spot and leakage site localization in order to complement the Liquid Crystal and Light Emission Microscopy techniques. The goal of this work was to produce a user-friendly and automated FMI system which is simple to use by the laboratory personnel. The instrumentation was set up on a probe station. It involved a uv light source, a dark box, a motorized optical microscope, a slow scan cooled CCD camera, a temperature controller, electrical test equipment, and a PowerMacintosh computer with IPLab software for instrumentation control, image acquisition and image processing. Software extensions for IPLab were developed with Think C to add automated functions to the system using the GPIB-IEEE 488 bus. IPLab scripts were written to fully automate instrumentation control, image acquisition and processing. A study of EuTTA compound fluorescence intensity variation with temperature, exposure time, and uv excitation was performed in order to characterize the system. The FMI technique was then applied to hot spot identification on microelectronic devices and failure analysis. With a few simple modifications, the same system was also employed for Light Emission Microscopy.

Body effect is the key characteristic of DRAM cell transistor. Conventional method uses a TEG structure for body effect measurement. But this measurement is not accurate, because TEG structure has only several transistors and it is located outside of the DRAM die. This paper suggests a viable method for measuring DRAM cell transistor body effect. It uses a memory test system for fast, massive, nondestructive measurement. Newly developed method can measure 100,000 DRAM cell body effects in two minute, without sample damage. The test gives one median value and 100,000 individual values of body effects. Median value of measured body effects is equal to the TEG body effect. An individual DRAM cell body effect has a correlation with the fin height.

In wafer fabrication (Fab), Fluorine (F) based gases are used for Al bondpad opening process. Thus, even on a regular Al bondpad, there exists a low level of F contamination. However, the F level has to be controlled at a lower level. If the F level is higher than the control/spec limits, it could cause F-induced corrosion and Al-F defects, resulting in pad discoloration and NSOP problems. In our previous studies [1-5], the theories, characteristics, chemical and physical failure mechanisms and the root causes of the F-induced corrosion and Al-F defects on Al bondpads have been studied. In this paper, we further study F-induced corrosion and propose to establish an Auger monitoring system so as to monitor the F contamination level on Al bondpads in wafer fabrication. Auger monitoring frequency, sample preparation, wafer life, Auger analysis points, control/spec limits and OOC/OOS quality control procedures are also discussed.

Failure Analysis (FA) process improvement is vital to cope with increasing demand on FA cycle time reduction from end customer. Real time failure analysis update, equipment usage data collection, and equipment security enhancement plays significant factor on cycle time reduction. This paper aims to discuss the barcode equipment management system in aiding FA Lab for process improvement.

This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

This paper describes a new technique, called the Light-Induced State Transition (LIST) method, that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows the user to locate a low signal line shortcircuited to a GND bus (or a high signal line shortcircuited to a VDD bus) in stand-by condition, which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by a experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS failure analysis, and has proved useful for finding a failure location rapidly.

In the process of fabricating high density mounting boards, locating faults in boards rejected in a functional test requires special circuit knowledge and skills, so it has been becoming more and more difficult to find the faults in a limited time. To address this problem, we have developed an Auto-Fault-Locating-System for mounting boards using a simple comparison technique and faulty net tracing algorithm. In the system, net-propagated faults are detected by comparing pulse-counts and voltages in good boards and faulty ones under full power supply. Faulty nets, which include the fault origin, are detected by tracing backward via a faulty propagation path using the input-output attribute of terminals. Measurements require 2.5 seconds per net (i.e., about 40 minutes for 1,000 nets), and searching faulty nets requires 10-20 seconds. The system successfully located the fault origin in 22 out of 25 boards rejected in a functional test. The located fault origins were found to be IC problems, pattern errors, open terminals and shorts between nets.

Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.

Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations are the same for the failed devices. From a statistical lot analysis, it is found that the short failure rate is higher for devices with thinner interlayer dielectric films. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.

The corrosion effect of an I2 background during focused ion beam (FIB) analysis of Cu-metallization structures is investigated. In-situ Cu corrosion in the FIB system can occur even if the I2 gas has not been used anymore in the last 24 h before the loading of the Cu sample in the system including several vents and pump-downs of the chamber in that period. Hence the I2 can have a long-term memory effect and is not compatible with FIB analysis or modification of devices with Cu metallization. Compositional and structural analysis shows that the reaction product is CuI.

Surface changes of copper and copper coupons coated with organic solderability preservative (OSP) after accelerated aging were measured using UV Differential Reflectance Spectroscopy. A chemometric method has been developed that allows correlation of the spectroscopic results with independent measurements of the solderability of the copper and copper/OSP coupons using a wetting balance or sequential electrochemical reduction analysis (SERA). Based on the results of this study, a versatile instrument for the assessment of the solderability of printed wiring boards has been demonstrated. The instrument is currently in beta testing at several locations.

Communication Signal Processors (CSP) did not have the Signal-to-noise ratio (SNR) performance expected. Significant differences were noticed between SNR values at wafer level and package testing. The analog section of the chip was suspected to be the culprit as the problem existed at the analog to digital conversion level. A Dielectric Altering Compound (DiAC) was chosen to simulate the packaged environment in decapsulated parts[1]. The DiAC was applied in and around the analog section, after application in other areas did not show the SNR degradation. The sampling capacitors in the A to D Converter section (ADC) were selectively coated with DiAC and laser trimmed to identify the offending circuit element. A signal trace running adjacent to the sampling caps, was isolated and suspected of coupling noise to the sampling caps. A FIB system was used to deposit a grounded metal shield that covered the suspect runner on a packaged part - subsequent testing showed no degradation. The above procedure was successful in isolating, verifying, and rectifying the SNR degradation. The SNR degradation was found on more than one code. The same procedure was used repeatedly on subsequent errant codes. Finally, a mask level fix on silicon achieved the desired SNR performance for all the codes.

With the arrival of flip-chip packaging, present tools and techniques are having increasing difficulty meeting failure-analysis needs. Recently a magneticfield imaging system has been used to localize shorts in buried layers of both packages and dies. Until now, these shorts have been powered directly through simple connections at the package. Power shorts are examples of direct shorts that can be powered through connections to Vdd and Vss at the package level. While power shorts are common types of failure, equally important are defects such as logic shorts, which cannot be powered through simple package connections. These defects must be indirectly activated by driving the part through a set of vectors. This makes the magnetic-field imaging process more complicated due to the large background currents present along with the defect current. Magnetic-field imaging is made possible through the use of a SQUID (Superconducting Quantum Interference Device), which is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current-density distribution in the sample can then be calculated from the magnetic-field image revealing the locations of shorts and other current anomalies. Presented here is the application of a SQUID-based magnetic-field imaging system for isolation of indirect shorts. This system has been used to investigate shorts in two flip-chip-packaged SRAMs. Defect currents as small as 38 μA were imaged in a background of 1 A. The measurements were made using a lock-in thechnique and image subtraction. The magnetic-field image from one sample is compared with the results from a corresponding infrared-microscope image.

Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.