Boundary-scan is a technology that’s been around for over ten years and is delivering the results foreseen by the IEEE working group that developed the 1149.1 specification. Many SMT (surface mount) production lines around the world use boundary-scan to solve the testing challenges presented by today’s complex designs. These users are realizing the vision of the specification, using it to restore test access and fault coverage to assemblies with few physical test points relative to the number of electrical nets to be tested. As the boundary-scan standard has gained acceptance and credibility, users, chip vendors and tools providers have developed important extensions of the original vision. Among the extensions already available or under active consideration is the use of boundary-scan for analog testing, concurrent programming of multi-vendor cPLD’s, dynamic verification of high-speed communication channels, and application within higher-level electronic assemblies beyond printed circuit boards i.e. to subsystems and systems. This paper describes the effectiveness of boundaryscan at the system level, focusing on the use of IEEE Std. 1149.1 compatible devices and ATPG tools to accomplish system level testing and in-system configuration.

The use of a scanning probe microscope (SPM), such as a conductive atomic force microscope (C-AFM) has been widely reported as a method of failure analysis in nanometer scale science and technology [1-6]. A beam bounce technique is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for a beam bounce also gives rise to the photoelectric effect while we are measuring the electrical characteristics of a device, such as a pn junction. In this paper, the photocurrent for a device caused by photon illumination was quantitatively evaluated. In addition, this paper also presents an example of an application of the C-AFM as a tool for the failure analysis of trap defects by taking advantage of the photoelectric effect.

This paper provides details of a novel method developed to cover a tiny epoxy layer as an intermediate buffer on the site-specific surface defect using a micro-bush on the tip of a glass needle in a plucking system without sample surface damage and localization problems. It describes the method and some real cases. The microstructures are investigated using an FEI Tecnai TF20 field emission gun transmission electron microscopy equipped with a high angle annular dark field detector, an energy dispersive X-ray spectroscopy, and Gatan image filter systems. The paper explains the micro-brushes and buffer layer preparation though figures and illustrations.

With the growing variety, complexity and market share of 3D packaged devices, package level FA is also facing new challenges and higher demand. This paper presents Lock-In Thermography (LIT) for fully non-destructive 3D defect localization of electrical active defects. After a short introduction of the basic LIT theory, two slightly different approaches of LIT based 3D localization will be discussed based on two case studies. The first approach relies on package internal reference heat sources (e.g. I/O-diodes) on different die levels. The second approach makes use of calibrated 3D simulation software to yield the differentiation between die levels in 8 die µSD technology.

This paper describes the successful effort to develop the Time Domain Reflectometry (TDR) tool by automating the equipment process. The current challenges in the tool usage brought about by miniaturization in the package technology presented itself as an opportunity for the tool improvement. The authors were able to devise an automated TDR system which is ergonomically safe, yielded a significant through put time reduction and provide a consistent and accurate result. This comes at a lower cost in comparison to the current system available in the Virtual Factory (VF).

Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful technical development, it is necessary to have a high speed interface that is complicated between the main processor and each IP block, but this can be problematic when the interface must support system level functions even though each IP alone does not have any problem. Most semiconductor companies and those doing Failure Analysis (FA) have adopted Automatic Test Equipment (ATE) because of its efficiency, but in cases where faulty products are detected at the customer site with their specific set of operating functions, the FA engineers have difficulties because of the challenge to convert customer’s functions to ATE test functions. To get through such a difficult situation, this paper presents a novel FA solution, utilizing Laser Voltage Probing (LVP) and set evaluation software and hardware, instead of ATE. This new FA technique can reduce the time to solve a system level application problem, improve FA quality with accurate timing analysis (detecting a 400ps signal glitch) and meet customer satisfaction by improving product quality. Fundamentally, the results of this paper compensated for the weakness in design procedures of IP blocks or products by adopting an additional simulation tool, which should prevent the recurrence of same-type errors.

Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.

Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations are the same for the failed devices. From a statistical lot analysis, it is found that the short failure rate is higher for devices with thinner interlayer dielectric films. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.

The corrosion effect of an I2 background during focused ion beam (FIB) analysis of Cu-metallization structures is investigated. In-situ Cu corrosion in the FIB system can occur even if the I2 gas has not been used anymore in the last 24 h before the loading of the Cu sample in the system including several vents and pump-downs of the chamber in that period. Hence the I2 can have a long-term memory effect and is not compatible with FIB analysis or modification of devices with Cu metallization. Compositional and structural analysis shows that the reaction product is CuI.

Surface changes of copper and copper coupons coated with organic solderability preservative (OSP) after accelerated aging were measured using UV Differential Reflectance Spectroscopy. A chemometric method has been developed that allows correlation of the spectroscopic results with independent measurements of the solderability of the copper and copper/OSP coupons using a wetting balance or sequential electrochemical reduction analysis (SERA). Based on the results of this study, a versatile instrument for the assessment of the solderability of printed wiring boards has been demonstrated. The instrument is currently in beta testing at several locations.

Communication Signal Processors (CSP) did not have the Signal-to-noise ratio (SNR) performance expected. Significant differences were noticed between SNR values at wafer level and package testing. The analog section of the chip was suspected to be the culprit as the problem existed at the analog to digital conversion level. A Dielectric Altering Compound (DiAC) was chosen to simulate the packaged environment in decapsulated parts[1]. The DiAC was applied in and around the analog section, after application in other areas did not show the SNR degradation. The sampling capacitors in the A to D Converter section (ADC) were selectively coated with DiAC and laser trimmed to identify the offending circuit element. A signal trace running adjacent to the sampling caps, was isolated and suspected of coupling noise to the sampling caps. A FIB system was used to deposit a grounded metal shield that covered the suspect runner on a packaged part - subsequent testing showed no degradation. The above procedure was successful in isolating, verifying, and rectifying the SNR degradation. The SNR degradation was found on more than one code. The same procedure was used repeatedly on subsequent errant codes. Finally, a mask level fix on silicon achieved the desired SNR performance for all the codes.

With the arrival of flip-chip packaging, present tools and techniques are having increasing difficulty meeting failure-analysis needs. Recently a magneticfield imaging system has been used to localize shorts in buried layers of both packages and dies. Until now, these shorts have been powered directly through simple connections at the package. Power shorts are examples of direct shorts that can be powered through connections to Vdd and Vss at the package level. While power shorts are common types of failure, equally important are defects such as logic shorts, which cannot be powered through simple package connections. These defects must be indirectly activated by driving the part through a set of vectors. This makes the magnetic-field imaging process more complicated due to the large background currents present along with the defect current. Magnetic-field imaging is made possible through the use of a SQUID (Superconducting Quantum Interference Device), which is a very sensitive magnetic sensor that can image magnetic fields generated by magnetic materials or currents (such as those in an integrated circuit). The current-density distribution in the sample can then be calculated from the magnetic-field image revealing the locations of shorts and other current anomalies. Presented here is the application of a SQUID-based magnetic-field imaging system for isolation of indirect shorts. This system has been used to investigate shorts in two flip-chip-packaged SRAMs. Defect currents as small as 38 μA were imaged in a background of 1 A. The measurements were made using a lock-in thechnique and image subtraction. The magnetic-field image from one sample is compared with the results from a corresponding infrared-microscope image.

Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

The Fluorescent Microthermal Imaging (FMI) technique was developed as a new failure analysis tool for hot spot and leakage site localization in order to complement the Liquid Crystal and Light Emission Microscopy techniques. The goal of this work was to produce a user-friendly and automated FMI system which is simple to use by the laboratory personnel. The instrumentation was set up on a probe station. It involved a uv light source, a dark box, a motorized optical microscope, a slow scan cooled CCD camera, a temperature controller, electrical test equipment, and a PowerMacintosh computer with IPLab software for instrumentation control, image acquisition and image processing. Software extensions for IPLab were developed with Think C to add automated functions to the system using the GPIB-IEEE 488 bus. IPLab scripts were written to fully automate instrumentation control, image acquisition and processing. A study of EuTTA compound fluorescence intensity variation with temperature, exposure time, and uv excitation was performed in order to characterize the system. The FMI technique was then applied to hot spot identification on microelectronic devices and failure analysis. With a few simple modifications, the same system was also employed for Light Emission Microscopy.

This paper describes a new technique, called the Light-Induced State Transition (LIST) method, that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows the user to locate a low signal line shortcircuited to a GND bus (or a high signal line shortcircuited to a VDD bus) in stand-by condition, which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by a experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS failure analysis, and has proved useful for finding a failure location rapidly.

Magnetic field imaging (MFI) has been an excellent tool for a low resistance failure localization in LSI devices. A Superconducting Quantum Interference Device (SQUID) and a Giant Magneto Resistive (GMR) sensor are well known in this field. A SQUID has extremely high magnetic sensitivity (500 nA, <40 pT/ √Hz)[1], but the spatial resolution is somewhat problematic due to the clearance that is needed for cooling and vacuuming mechanism. A GMR sensor has higher resolution but lower sensitivity (50 uA, <10 nT/√Hz)[1] and, they have less flexibility because the sensor/stage has to be scanned during operation. In this paper, we present a new current imaging method called Magneto-Optical (MO) Frequency Mapping (MOFM). The imaging is based on a laser beam scanning, which allows flexibility and ease of use. The MO signal intensity is inversely proportional to the distance between the sensor and the current path to be detected. Since it can be 10 um or less, i.e., one half of the MO crystal thickness, it practically makes the MOFM’s system sensitivity is 10 uA, it only 20 times lower than a SQUID method, even though the intrinsic sensitivity may be about 250 times or so lower. It can also achieve high special resolution as with the GMR sensor because of the short distance or clearance needed to sense the current. These characteristics are verified with a TEG sample and we present a case in which it is applied for the short circuit failure localization.

Many articles and books have been written that discuss and study the techniques of lean thinking and methodologies. The applications of these methodologies have included such industries as manufacturing, health care, and information technology. Application to analytical laboratories has been rare or non-existent due to the inability to apply lean methodologies to a process with ‘unique’ analytical work flows as well as a lack of a direct connection to the manufacturing value stream. The following paper describes the work done in a semiconductor failure analysis laboratory to visualize work flow, design a forecasting model, and create a management system. The result of which has been sustained and improved quality, resource utilization, and delivery of actionable root cause failure analysis.

Failure analysis at the system level requires a well-defined process and methodology in order to drive quality improvements onto motherboards or other subsystems of a personal computer. This process needs to be structured around the type of failure mechanisms that an FA group desires to understand. This paper discusses a specific case study involving electrical overstress in a personal computer that impacted the motherboard of the system. The case study resulted in a solution to increase quality on motherboards in the context of electrical overstress prevention.

This paper reports on a setup and a method that enables automated analysis of mechanical stress impact on microelectromechanical systems (MEMS). In this setup both electrical and optical inspection are available. Reliability testing is possible on a single chip as well as on the wafer level. Mechanical stress is applied to the tested structure with programmable static forces up to 3.6 N and dynamic loads at frequencies up to 20 Hz. The applications of the presented system include the postmanufacturing test, characterization and stress screens as well as reliability studies. We report preliminary results of long-term reliability testing obtained for a CMOS-based stress sensor.

Existing tools used by industry to manually remove PCB components for disbond type mapping or crack area measurement present significant ergonomic and process quality concerns. The most common tool designs often cause damage to some of the solder joints on components during pull, and frequently, operators using these designs report safety concerns. This paper evaluates these concerns and proposes a design solution that eliminates them. With a manual T-handle pull tool system introduced here, there is no prying, lever or angular force applied to remove the component. The pull tool rotates using vertical threads to apply vertical removal force. It demonstrates a reduction in manual operator force by an average of 93% compared to the cam lobe lever design. Additionally, the pull tool reduces bending of pull bolts and angular pull direction that may interfere with availability and interpretation of subsequent disbond data.