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stuck-at faults

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Proceedings Papers

ISTFA1996, ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis, 127-132, November 18–22, 1996,
... equivalence classes are indicative of a less precise diagnosis. Even though high precision may not be achieved for non-stuck-at defects, the model and heuristic should effectively diagnose defects other than stuck-ats. It should also be able to do so for any pattern or location on the chip. In our experiment...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 585-594, November 14–18, 2004,
... many stuck-at faults, a parametric analysis is needed to identify which defect mechanism is the cause of a cache failure. Pico-probing is the most common method of parametric analysis on SRAM cells, but is becoming increasingly difficult on smaller geometries. These curves can also be taken non...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 477-483, November 14–18, 1999,
... properties, and finally some results from 0.25 and 0.18 micron technologies. debugging flip-chip microprocessors integrated circuits silicon microsurgery stuck-at fault 477 Advanced Micro-Surgery Techniques and Material Parasitics for Debug of Flip-Chip Microprocessor Rick Livengood, Paul Winer...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 93-103, October 28–November 1, 2018,
...Abstract Abstract We present the first experimental demonstration of stuck-at scan chain fault isolation through the exploitation of Single Event Upsets (SEU) in a Laser-Induced Fault Analysis (LIFA) system. By observing a pass/fail flag, we can spatially map all flops after a defect...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 723-732, November 3–7, 2002,
...-at and timing failures (transition faults and hold time faults). The experimental results based on simulation and silicon units for several products show the effectiveness of the proposed method. failure analysis fault diagnosis scan chain silicon stuck-at faults A New Technique for Scan Chain...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 369-376, October 31–November 4, 2021,
... during nano-probing. would also like to thank the following people for their help during ATE data characterization and diagnostics: Chandra Gandu, Jie Sun, Martin Parley, Krishna Vemuri, Jacobe Labog and Dilbagh Singh. VII. References [1] K. Y. Mei, Bridging and stuck-at faults, IEEE Trans. Comput...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 510-516, November 6–10, 2005,
... shrinking fabrication processes. In this paper, we present a new scan chain diagnosis procedure that is centered on Load Pass Unload Fail/Load Fail Unload Pass (LPUF/LFUP) and Scan Shift Logic State Mapping (SSLSM) techniques to isolate both stuck-at and timing scan chain faults without the design overhead...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 389-396, November 14–18, 1999,
... (for example, Mapping Opens Shorts Stuck- ats Other Signal Shorts Opens Stuck-ats Defect Space Stuck-at Space 393 an open on signal A). Figure 5 shows the composite construction for a signal line (a.k.a node). The union of all the outputs that fail due to a stuck-at 0 and a stuck-at 1 fault at signal A is used...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 509-519, November 11–15, 2012,
... transistor number of a circuit, thus the proposed approach can be applied to real designs. In this paper we present our effect-cause intra-cell diagnosis approach. Three types of fault models are considered: (i) the stuck-at fault, (ii) the dominant bridging fault and (iii) the open fault (resistive...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 171-175, November 5–9, 2017,
...Abstract Abstract Laser Voltage imaging (LVI) is an established and widely used technique for isolating scan chain failures, especially those that are stuck-at a particular state. Enhancements such as second harmonic mapping have been beneficial in detecting a fault that is not stuck...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 496-505, November 2–6, 2003,
... traditionally focused on fault localization. The logic locations identified by diagnosis are then mapped to physical locations that a PFA engineer can examine. Classical diagnosis based on the single stuck-line (SSL) fault model as well as the more recent approaches like the one presented in [3] target...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 449-459, October 28–November 1, 2018,
..., Automated Test Pattern Generation (ATPG) can be used to control the logic on internal nodes in the digital core in such a way that it could test for internal faults depending on the fault model used. Stuck- at fault model is used to test nets/ports for stuck-at 1 (sa1) or stuck-at 0 (sa0). Transition...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 47-51, November 14–18, 2004,
... of the fault and the X/Y coordinates of the suspects. Our fault diagnosis method is based on the stuck-at fault simulation results, which are combined towards more complex fault models and a ranking procedure to increase the precision. It consists of two major steps: identification of the faulty nets...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 182-191, November 10–14, 2019,
... location. Case Study 1 Both failing devices used in this case study were failing for excessive IDDQ currents while all other ATPG patterns (Stuck at, bridging, and transition delay) were passing. Testing on ATE and on a compact test HW confirmed the IDDQ failure. Table 3: IDDQ current for the different...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 191-196, November 14–18, 2004,
... tied to a logic 0 or 1 (e.g. Ground, Power, or their equivalent). Otherwise the DACS can be modeled with a stuck-at-0 or stuck-at-1 fault at the scan chain signal. In this scenario, it is easy to locate the DACS in the scan chain, but the candidate set may be too large at the system logic end...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 397-401, November 3–7, 2002,
... Method I. Stuck at Fault Vector This method uses a function generator as a system clock with 1 MHz input to do the dynamic testing, stopping at the failed address reported from auto test equipment. The leakage current of the core power is monitored to see if it goes up. If not, the input state is changed...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 52-57, November 14–18, 2004,
... scan chain (i.e. a scan chain with a stuck-at-fault). Scan chain design and diagnostics The scan-based design is one of the fundamental Design-For- Test (DFT) features that are widely used in modern VLSI designs because it simplifies the test patterns generation and reduces the chip debug time...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 180-187, November 2–6, 2008,
.... In this case, the reset pattern should 1 3 2 Laser Pulse Trigger scan-out DUT input stimuli ATE Scanner Image Processing Unit Detector Laser DALS Kit Digital Oscilloscope 181 come out. But if there is a defect, the faulty pattern will be shifted out indicating the location of the stuck-at fault. One can only...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 181-190, November 14–18, 2004,
... diagnosis. We identified several deficiencies in these tools: 1. Most off-the-shelf tools use the stuck-at fault model. Although the stuck-at fault model may generate patterns that detect defects more complex than the fault model itself, its use during diagnosis may not pinpoint the location of a complex...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 86-90, November 13–17, 2011,
... be simulated using a stuck-at fault simulator by defining the defect excitation conditions, and the locations in the logic model where stuck-at faults must be injected to simulate the defect behavior. For example, a bridge defect between two nets is excited when the nets are driven to opposite logic values...