A method to measure “on site” programmed charges in EEPROM devices is presented. Electrical Scanning Probe Microscopy (SPM) based techniques such as Electric Force Microscopy (EFM) and Scanning Kelvin Probe Microscopy (SKPM) are used to directly probe floating gate potentials. Both preparation and probing methods are discussed. Sample preparation to access floating gate/oxide interfaces at a few nanometers distance without discharging the gate proves to be the key problem, more than the probing technique itself. Applications are demonstrated on 128 kbit EEPROMs from ST Microelectronics and 64 kbit EEPROMs from Atmel.

This paper presents a judicious reasoning method by coupling passive voltage contrast (PVC) with scanning probe microscopy (SPM) for revealing particular invisible defect modes, which were imperceptible to observe and very difficult to identify by means of traditional physical failure analysis techniques. In order to certify this compound method, it is applied to an implant issue as a case study. Through solving this particular defect mode, whose exact failure position could not be determined even with the most sensitive PVC or high-resolution SPM current mapping, the procedures and contentions are illustrated further. The significance of the reasoning method is based on electrical characterization and differential analysis. By coupling PVC with SPM, the capability to identify tiny defects is not limited to just distinguishing leakage or high-resistance under contacts. PVC can detect abnormal N+ contacts due to improper implanting, and SPM can provide the precise electrical characteristics.

This paper describes novel concepts in equipment and measurement techniques that integrate optical electrical microscopy and scanning probe microscopy (SPM) capabilities into a single tool under the umbrella of optical nanoprobe electrical (ONE) microscopy. Optical imaging ONE microscopy permits non-destructive measurement capability that was lost more than a decade ago, when the early metal levels became electrically inaccessible to microprobers. SPM imaging techniques do not have sensitivity to many types of defects, and nanoprobing all of the transistors in an area pinpointed by optical electrical microscopy is often impractical. Thus, in many cases, ONE microscopy capability will permit analytical success instead of failure.

Physical failure analysis of nanoelectronic devices is typically performed using plan view or cross-sectional TEM, SEM or SPM techniques. While plan view SPM and SEM analyses are limited by the depth sensitivity of the technique, cross-sectional analysis requires at least approximate localization of the fail location within the device for effective sample preparation. Multi-finger wide 2D planar devices and multi-FIN 3D devices are structures which require an additional step in pinpointing the fail area within the device. This paper describes successful use of EBIC/EBAC techniques to localize the fail location within such devices in both the 22 nm and 14 nm technology nodes.

As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

In 1986 the Atomic Force Microscope (AFM) was invented by Gerd Binnig, Christoph Gerber, and Calvin Quate [1]. Since then, numerous analytical techniques have been developed and implemented on the AFM platform, evolving into what is collectively called the Scanning Probe Microscope (SPM). The SPM has since become well established as a mainstream analytical instrument with a continually increasing role in the development of nanoscale semiconductor technologies providing critical data from initial concept to technology development to manufacturing to failure analysis [2]. Scanning Capacitance Microscopy (SCM) has a longstanding, well-established track record for detecting dopant-related mechanisms that adversely affect device performance on planar (Field Effect Transistor) FETs as well as other structures (e.g., diodes, capacitors, resistors). The semiconductor industry’s transition to three dimensional FinFET devices has resulted in many challenges with regard to device analysis. This is especially true when it is necessary to perform detailed dopant analysis on a specific device; the device may be comprised of a single or multiple fins that have been called out specifically through traditional fault localization techniques. Scanning Capacitance Spectroscopy (SCS) is an analytical method, implemented on the SCM platform in which a series of DC bias conditions is applied to the sample and the carrier response is recorded using SCM [3]. SCS has a proven history of highlighting dopant related anomalies in semiconductor devices, which, in some instances, might not otherwise be “visible”. This paper describes successful application of SCM and SCS in showing, in full detail, a dopant-related failure mechanism on an individual, location-specific 14 nm FinFET.

Nondestructive observation of domain structure of ferroelectrics, dynamic behavior under external field and related phenomena is becoming significant. As a nondestructive and subsurface characterizing technique, the authors developed acoustic microscopy based on a commercial scanning probe microscope for direct observation of local ferroelectricity, elasticity and defects on several inorganic functional materials, transparent PLZT ceramics, relax-based PMN-PT crystal and lead-free bismuth titanate ceramics without any special processing (polishing or etching) to the sample. The direct observation is particularly useful and convenient for analyzing ferroelectrics/semiconductor integrated material and devices. The excitation frequency is in the range of several kHz to decades of kHz, which is much lower than that of the traditional acoustic imaging techniques. But several applications of scanning probe acoustic microscope (SPAM) involving ferroelectric samples with the resolution of 10nm were obtained. The expanding scope of application for SPAM shows exciting possibilities for non-destructive analyses in the microelectrics industry.

We present a characterization methodology for fast direct measurement of the charge accumulated on Floating Gate (FG) transistors of Flash EEPROM cells. Using a Scanning Electron Microscope (SEM) in Passive Voltage Contrast (PVC) mode we were able to distinguish between '0' and '1' bit values stored in each memory cell. Moreover, it was possible to characterize the remaining charge on the FG; thus making this technique valuable for Failure Analysis applications for data retention measurements in Flash EEPROM. The technique is at least two orders of magnitude faster than state-of-the-art Scanning Probe Microscopy (SPM) methods. Only a relatively simple backside sample preparation is necessary for accessing the FG of memory transistors. The technique presented was successfully implemented on a 0.35 μm technology node microcontroller and a 0.21 μm smart card integrated circuit. We also show the ease of such technique to cover all cells of a memory (using intrinsic features of SEM) and to automate memory cells characterization using standard image processing technique.

The passive voltage contrast (PVC) in this experiment was widely used to detect open/short issues for most failure analyses. However, most of back-end particles were visible, but front-end particles were not. And sometimes only used PVC image, the failure mechanism was un-imaginable. As a result, we needed to collect some electrical data to explain complex PVC image, before physical failure analysis (PFA) was started. This paper shows how to use the scanning probe microscope (SPM) tool to make up PVC method and overcome the physical failure analysis challenge. From our experiment, the C-AFM could provide more information of the defect type and give faster feedback to production lines.

Scanning microwave impedance microscopy (sMIM) is an emerging technique that can provide detailed information beyond that of conventional scanning capacitance microscopy (SCM), and other electrical scanning probe microscopy (SPM) techniques, for the investigation and failure analysis (FA) of semiconductor devices. Integration of new dielectric materials at lower levels of the device structure with the need for quantification of dielectric and dopants in semiconductor devices with sub-micron spatial resolution pushes the practical boundaries of typical atomic force microscopy (AFM) electrical modes. sMIM can measure both linear and non-linear materials (insulators and doped semiconductors, respectively) simultaneously. sMIM has a linear response to log k (dielectric number) and log N (doping concentration) making it an ideal method for providing quantitative measurements of semiconductor devices over a large range of values. This work demonstrates an example of a practical application of sMIM for quantitative measurement of the dopant concentration profile in production semiconductor devices. A planar dopant calibration sample is used to calibrate the sMIM prior to performing the measurements on an “unknown” production device. We utilize nanoscale C-V data to establish a calibration curve for both n- and p-type carriers and apply the calibration curve to an “unknown” device, presenting the measurements in units of doping concentration.

Scanning capacitance microscopy (SCM) is an SPM technique which measures capacitance variation between tip and sample generated by applied AC bias while the tip is scanning in contact mode. Focused ion beam (FIB) milling is the more precise method to perform cross-sectioning of a specific site. The surface amorphization and charge trap layers formed during FIB machining affect the SCM dC/dV signal. This article demonstrates that micro-cleaving and FIB milling are capable of preparing a cross-sectional sample for 2D doping profiling of a specific site for SCM observation. Using the Micro-cleaving technique, a cross-sectional sample can be prepared easily with higher accuracy and shorter time than using a polishing method. However, Micro-cleaving can't be used by itself in the case of cross-sectioning a pattern formed by front end processing of sub-micron patterns. The FIB technique can assist the Micro-cleaving technique in cleaving of front end patterns.

In this paper, we present our recent applications of scanning capacitance microscopy (SCM) on specific devices with sampling window as small as 100nm. The dopant related root causes were successfully identified on those devices fabricated with 90nm CMOS technology. The key step in our approach is the development of a sample preparation technique that allows us to precisely x-section through a transistor without being affected by focused ion beam (FIB) artifacts. FIB was used to mark the area of interest with high precision, but it did not expose the devices of interest. Optical microscope and atomic force microscope (AFM) were used to inspect the mechanically polished surface, thus avoiding beam effects from FIB or SEM. In the first application, a doping anomaly was identified in a PFET poly gate, in a single bit failed SRAM cell. In the second application, an asymmetry of a PWell implant profile in a window of 150nm was identified as the cause of leakage in a capacitor array. Our approach may be applied to other scanning probe microscopy (SPM) techniques in the same category, i.e., scanning spreading resistance microscopy (SSRM) or scanning microwave microscopy (SMM).

The use of a scanning probe microscope (SPM), such as a conductive atomic force microscope (C-AFM) has been widely reported as a method of failure analysis in nanometer scale science and technology [1-6]. A beam bounce technique is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for a beam bounce also gives rise to the photoelectric effect while we are measuring the electrical characteristics of a device, such as a pn junction. In this paper, the photocurrent for a device caused by photon illumination was quantitatively evaluated. In addition, this paper also presents an example of an application of the C-AFM as a tool for the failure analysis of trap defects by taking advantage of the photoelectric effect.

In recent years, scanning probe microscopy (SPM) has drawn substantial attention for subsurface imaging, since the ultrasharp AFM tip (≈ 10 nm in radius) can deliver and detect, mechanical and electrical signals right above the material’s 3D volume with which it is directly interacting. Electrostatic force microscopy, or EFM, is one of the most common atomic force microscopy (AFM) variants for electrical property characterization. In this work, we demonstrate a method to significantly improve EFM’s subsurface imaging capability. Unlike conventional EFM, where an AC bias is applied to the cantilever, we applied two out of phase AC biases to adjacent subsurface lines and image the resulting cantilever response at the surface. The resulting remote bias induced EFM (RB-EFM) amplitude shows decent contrast of metal lines with a 2.4 μm spacing buried up to 4 μm beneath the surface. This novel method may resolve lines with a horizontal spacing of less than 130 nm at such depth and wider lines to at least 6 μm in depth. In addition, the results are compared with conventional EFM and KPFM that detects subsurface structure with two independent DC biases. A COMSOL simulation model has been developed that reproduces the essential features of the measurement and explains the improvement of subsurface imaging with RB-EFM compared to other electrostatic force imaging techniques. We show, that by biasing independent lines at a small delta in frequency from the cantilever resonance, multiple line traces can be differentiated in the RB-EFM image.

Advances in semiconductor technology are driving the need for new metrology and failure analysis techniques. Failures due to missing, or misregistered implants are particularly difficult to resolve. Two-dimensional implant profiling techniques such as scanning capacitance microscopy (SCM) rely on polish preparation, which makes reliably targeting sub 0.25 um structures nearly impossible.[1] Focused ion beam (FIB) machining is routinely used to prepare site-specific cross-sections for electron microscopy inspection; however, FIB induced artifacts such as surface amorphization and Ga ion implantation render the surface incompatible with SCM (and selective etching techniques). This work describes a novel combination of FIB machining and polish preparation that allows for site-specific implant profiling using SCM.

Listings of the EDFAS 2004-2005 Board of Directors, the ISTFA 2004 Organizing Committee Program Chairs, and other contributors and committee members.

The use of scanning kelvin probe microscopy (SKPM) for analyzing two-dimensional dopant profiles on production-level silicon CMOS devices is described, with images of topography and dopant profiles presented. Both plan-view and crosssectional analyses are performed to measure CMOS device effective channel length (Leff), source-drain and well-junction depths. SKPM data not only tracked variations in Leff but uncovered anomalies in dopant that were responsible for device failure. For example, a nonfunctional ring-oscillator in a 0.25μm technology was debugged with SKPM. Details of sample preparation and the fabrication of durable, highly conductive (silicided) silicon kelvin probe tips which are key to acquiring reproducible, consistent data is also given.

Visualization of dopant related anomalies in integrated circuits is extremely challenging. Cleaving of the die may not be possible in practical failure analysis situations that require extensive electrical fault isolation, where the failing die can be submitted of scanning probe microscopy analysis in various states such as partially depackaged die, backside thinned die, and so on. In advanced technologies, the circuit orientation in the wafer may not align with preferred crystallographic direction for cleaving the silicon or other substrates. In order to overcome these issues, a focused ion beam lift-out based approach for site-specific cross-section sample preparation is developed in this work. A directional mechanical polishing procedure to produce smooth damage-free surface for junction profiling is also implemented. Two failure analysis applications of the sample preparation method to visualize junction anomalies using scanning microwave microscopy are also discussed.

Scanning capacitance microscopy (SCM) is a powerful technique that may readily be applied to semiconductor failure analysis yielding information on problems stemming from doping issues. This paper details the study of a current leakage failure and outlines the use of the SCM technique for shallow trench isolation applications. A two-step sample preparation technique involving firstly, Chemical Mechanical Polishing (CMP) followed by a wet etch, could improve the sample surface planarization allowing SCM inspection of the STI region.

The transistor structure of memory devices and other cutting-edge semiconductor devices has become extremely minute and complicated owing primarily to advances in process technology and employment of three-dimensional structures. Among the various approaches to improve the device performance and functionality, optimizing the carrier distribution is considered to be quite effective. This study focuses on scanning nonlinear dielectric microscopy (SNDM), a capacitance-based scanning probe microscopy technique. First, to evaluate SNDM's potential for high-resolution measurement, the most commonly used metal coated tip with a tip radius of 25 nm was used to measure a quite low-density impurity distribution. Then, after confirming that the SNDM's S/N ratio was sufficiently high for the smaller probe tip, an ultra-fine diamond probe tip with a nominal tip radius of lesser than 5nm as an SNDM probe tip to measure sub-20 nm node flash memory cell transistors was employed. Successful results were obtained and are reported.