Abstract Solder bumps are frequently the sites of defects that cause continuity failures in ceramic flip chip packages. In concurrent technology the solder bump is a multi-layered structure containing several interfaces. Conventional c-SAM imaging alone cannot delineate subtle bump defects. In this article we present experimental results that document the nature of interface defects in multi-layered solder bumps as well as their acoustic signatures. The acoustic signatures obtained from defective bumps are contrasted with the signals obtained from pristine bumps and the sensitive nature of these signatures to defects is highlighted.

Abstract In a previous contribution we highlighted the potential use of spectral analysis of acoustic signals reflected from solder bumps as a means to identify anomalies in the bump. With numerous interfaces in contemporary solder bump geometries, time domain interpretation of acoustic signals is not straightforward. Frequency domain analysis is hence another route to utilizing information contained about defects in acoustic signals emanating from suspect bumps. In this contribution we highlight the use of Wavelet transforms and power spectra in analyzing acoustic signals and demonstrate with a few examples how the transform may be used to obtain unique finger prints of anomalies. We also discuss how cross correlation technqiues may be used to classify a fingerprint once a comprehensive library of finger prints is empirically constructed.

Abstract Next generation assembly/package development challenges are primarily increased interconnect complexity and density with ever shorter development time. The results of this trend present some distinct challenges for the analytical tools/techniques to support this technical roadmap. The key challenge in the analytical tools/techniques is the development of non-destructive imaging for improved time to information. This paper will present the key drivers for the non-destructive imaging, results of literature search and evaluation of key analytical techniques currently available. Based on these studies requirements of a 3D imaging capability will be discussed. Critical breakthroughs required for development of such a capability are also summarized.

Abstract Signal processing and data interpretation in scanning acoustic microscopy is often challenging and based on the subjective decisions of the operator, making the defect classification results prone to human error. The aim of this work was to combine unsupervised and supervised machine learning techniques for feature extraction and image segmentation that allows automated classification and predictive failure analysis on scanning acoustic microscopy (SAM) data. In the first part, conspicuous signal components of the time-domain echo signals and their weighting matrices are extracted using independent component analysis. The applicability was shown by the assisted separation of signal patterns to intact and defective bumps from a dataset of a CPU-device manufactured in flip-chip technology. The high success-rate was verified by physical cross-sectioning and high-resolution imaging. In the second part, the before mentioned signal separation was employed to generate a labeled dataset for training and finetuning of a classification model based on a one-dimensional convolutional neural network. The learning model was sensitive to critical features of the given task without human intervention for classification between intact bumps, defective bumps and background. This approach was evaluated on two individual test samples that contained multiple defects in the solder bumps and has been verified by physical inspection. The verification of the classification model reached an accuracy of more than 97% and was successfully applied to an unknown sample which demonstrates the high potential of machine learning concepts for further developments in assisted failure analysis.

Abstract Presence of foreign materials (i.e, contamination) can affect the reliability of copper (Cu) bumps when it affects the wettability of the solder and consequently weakens the joint formation of the copper to the substrate. This paper looks at a case of non-wetting of Cu bumps due to silicon contamination induced during assembly processing. In this case study, surface roughness is the main factor being altered when foreign materials contaminate the metal substrate. Sample devices were tested in a resistive open unit and a direct current failing unit, respectively. It was found that the silicon dust present on the substrate in effect "roughens" the surface, thereby decreasing the wettability between the molten solder to the metal substrate. For future studies, it is recommended that the effect of reliability stress activities on the Cu bumps with silicon contaminations be examined to evaluate the risks for possible field failures of this defect.

Abstract This paper placed a strong emphasis on the importance of applying Systematic Problem Solving approach, deep dive and use of right/appropriate FA approach/tools that are essentially critical to FA analysts to understand the “real” root cause. A case of low yield with polar failing pattern was seen and matched well with the Al Pad etch E chuck configuration. Customer also reported of passivation crack issue at the solder bumps. All these evidences suggested the root cause was related to wafer fabrication issue. However, it was through a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach that led to uncover the actual root cause. Although customer test condition was not able to be duplicated due to limited information available in foundry industry, a four point probing alternative method was engaged to overcome this limitation. Unlike typical case, the AlOx thickness was comparable for bad and good dies. Further in depth analysis subsequently revealed the higher O content in the AlOx for the bad dies that was the real culprit for the higher bump resistance. This paper highlights the job of FA analyst is not simply finding defect but also plays a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically / physically) to Fab. It would serve as a good reference to wafer Fab that encountered such issue.

Abstract This article presents a step-by-step sample preparation method for the cross sectioning of silicon die in a ceramic package without the need for die removal or epoxy encapsulation. The sample preparation includes sawing the package, sample mounting to the polishing stub, and FIB cutting the area of interest and SEM Exam. In addition, a discussion on an automatic polishing method is included. This method is applicable for a broad range of silicon (Si) die package technologies and has also been successfully used on "TSOP" and state-of-the-art microprocessor packages which include the "organic" substrate, the Si die, and the massive copper die lid. The entire failure analysis is done at room temperature, eliminating any questions about sample preparation artifacts. Because the sample is imaged in the SEM at 90 degrees, much improved layer detail and voids microstructure is present in the final image.

Abstract The development of a next generation high-resolution x-ray Computed Tomography (CT) tool and its applications are reported in this paper. Some of the key features are region of interest capability, improved time-to-data, improved usability, and data collection automation capability. We also discuss the key technical challenges that are faced by x-ray CT technology. Critical cases that are hard or not possible to isolate by alternative methods are also discussed. Examples include Controlled Collapse Chip Connection (C4) bump cracking and “invisible” non-wetting analysis, ball grid array (BGA) solder joint cracking, and wirebond microcracking and wirebond shorting, as well as demonstration of progressive testing capability.

Abstract The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.

Abstract This paper describes a new diagnostic technique for analyzing microstructural changes occurring to flip chip joints after accelerated thermal tests. Flip chip reliability was assessed at high temperatures, with and without the application of electrical bias. A combination of standard metallurgical polishing techniques and the use of a focused ion beam (FIB) lift out technique was employed to make site-specific samples for transmission electron microscopy (TEM) cross-sections. We studied evaporated 95Pb/5Sn bumps, on sputtered Cr/CrCu/Cu/Au as the under bump metallization (UBM). Thermally stressed samples were tested for electrical continuity and evaluated using 50 MHz C-mode scanning acoustic microscopy (C-SAM). Failed samples were crosssectioned and large voids at the UBM were observed optically. TEM specimens taken from the predefined UBM region of degraded flip chip devices provided critical microstructural information, which led to a better understanding of a cause of degradation occurring in the flip chip joints.

Abstract This paper describes the detailed sample preparation of a solder joint at the level between a semiconductor package and board. Different sample preparation techniques are described and compared. Preparing and targeting a large sample area containing multiple solder bumps is discussed. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of strain is associated with the development of cracks and delamination at the solder joint interface.

Abstract The present paper is a study on flip-chip open bump failure mechanism. Initial electrical testing showed open circuit condition. Scanning acoustic microscope (C-SAM) identifies delamination on particular bump(s). Initial cross-sectional images suggested that the separation took place at Al – TiW interface. However, EDS analysis on the separated surface indicated the presence of Al metal at both sides of the separation, which raises a question of why the Al layer is cracked or separated instead of interface de-lamination. Research in literature and investigation at assembly line points an ultrasonic cleaning step in manufacturing process as a contributor to the open bump failure. Examining virgin dice after bump removal observed crack in nitride passivation around the bump neck, indicating high stress level during passivation film deposition and/or bump formation process. Hence it is concluded that ultrasonic cleaning in device assembly aggravates preexisting stress in weak bump(s), resulting in latent failure in field application.

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Abstract Advances in electronic packaging are fueled by the insatiable appetite that consumers have for bandwidth in mobile appliances. The technological answer to this demand is increase the interconnect count and shrink the pitch, solder volume and height. The features of interest and the defects in these packages are becoming increasingly smaller. Consequently, the characterization of these defects becomes more challenging due to the smaller size and new material structures. New package structures must pass the JEDEC standard tests and a critical part of qualifying new packages as products is proper identification of the root cause of failures. Therefore, innovative solutions to correct the fundamental problems in the development process enable new package solutions to be brought to the market. In this paper we describe an alternative failure analysis workflow involving X-ray microscopy which offers several advantages over standard imaging techniques. The nondestructive nature of x-ray microscopy enables engineers to image parts throughout the entire environmental stress cycle for more accurate determination of the root cause of failures. Additionally, a larger number of interconnects may be sampled, defect isolation in z direction for stacked die packages is made easier and subsequent imaging techniques may be used to complement the data. Both 3 dimensional images of defects as well as 2 dimensional cross sections will be shown to effectively analyze the true root cause of failures.

Abstract Modern day VLSI Semiconductor devices are manufactured using a chemical mechanical polish (CMP) process. The resultant layers are planar with respect to one another and should be easy to remove. All that needs to be done is to lap the layer until the region of interest is exposed. In practice this has been difficult. This article describes the combination of processes that are required to take full advantage of the strength of deprocessing techniques (lapping, plasma and gel controlled wet chemical deprocessing) to deliver a perfectly planar sample for inspection. A discussion on the thought process required to adequately select the proper chemicals for the gel controlled etch is given. Finally, a typical deprocessing flow is described. It is concluded that this combined solution enables planarity to be maintained across 100% of the device surface. There is less chance the failure site is damaged by the deprocessing.

Abstract With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.

Abstract This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

Abstract The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

Abstract This article describes how 3D Real Time X-Ray (RTX) technique enhances the capability of package-level failure analysis of a flip-chip package. 3D RTX was successful in detecting different failure signatures. This paper outlines detailed applications of 3D RTX with case studies.

Abstract Space Domain Reflectometry (SDR) is a newly developed non-destructive failure analysis (FA) technique for localizing open defects in both packages and dies through mapping in space domain the magnetic field produced by a radio frequency (RF) current induced in the sample, herein the name Space Domain Reflectometry. The technique employs a scanning superconducting quantum interference device (SQUID) RF microscope operating over a frequency range from 60 to 200 MHz. In this paper we demonstrate that SDR is capable of locating defective micro bumps in a flip-chip device.