We have developed a new scanning laser microscopy methodology, Soft Defect Localization (SDL), that directly locates soft defects from the front side and backside of an IC. The method combines localized laser heating with the pass/fail state of a device to successfully localize soft defects. Subtle, thermally sensitive soft defects can be localized by careful selection of the IC voltage, temperature, and operating frequency. Several examples are shown.

In this paper, we present application of the SDL technique towards full root cause analysis of functional and structural failures from BIST, SCAN etc. on AMD’s advanced Silicon-on-Insulator (SOI) microprocessors based on a 90 nm process technology node. The devices were exercised at speed using production testers. SDL is used on these microprocessors with failure modes which pass at a lower temperature/voltage but fail at higher temperature/voltage or vice versa to isolate the failing logic/node. The SDL sites are examined for a full root cause analysis and possible process improvements.

Dynamic Laser Stimulation (DLS) techniques for Soft Defect Localization (SDL) have been well documented for logic devices [1][2]. More recent literature has broadened the traditional SDL pass/fail mapping by employing multiple device parameters including power analysis [3], spectrum response [4], and other analog variations [5]. A practical and efficient implementation of SDL without the use of synchronization or traditional Automatic Test Equipment (ATE) hardware is presented. A dynamic way of analyzing many parameters of mixed signal and analog ICs can be obtained through the use of a high waveform rate oscilloscope, feedback loop, or discrete comparator. Multiple case studies are shown to illustrate the methodology.

A new localization method called LIA-SDL is introduced and applied to scan shift problems. The method combines local thermal stimulation technique with lock-in technique applied to periodical test pattern. The localization capability on soft defects is shown in comparison with SDL. Same localization results are obtained. LIA-SDL technique requires no special LSM (Laser Scan Microscope) facilities and is quite easy to handle. Limits and prospects of this new methodology are shown at several analysis examples.

In this paper, we describe a modified soft defect localization (SDL) technique, PSDL (pseudo-soft defect localization), to localize pseudo-soft defects in integrated circuits (ICs). Similar to soft defects, functional failures due to pseudo-soft defects are sensitive to operating parameters (such as voltages, frequencies and temperatures) and/or laser exposures. Pass/fail states in pseudo soft defect failures are, however, not fully reversible after laser exposure or after changing operating parameters. PSDL uses the methodology of conventional SDL and/or TIVA in combination with a new scanning scheme for defect localization. An example will be shown to demonstrate the use of this technique to localize pseudo-soft defects.

Equipment manufacturers have developed peripherals for their tools that add soft defect localization (SDL) capability to existing optical beam tools, in many cases providing excellent results. However, these upgrades add significant cost to the tool. This paper presents the design considerations for a simple adapter that was developed in house to add SDL capability to optical beam induced resistance change (OBIRCH) tool, including resolution of some unexpected problems. This solution represents a simple, low cost method to add SDL testing capability to the OBIRCH tool and can also be used in conjunction with OBIC and XIVA tools with little or no modification. An early example of the SDL results provided by this adapter is also presented.

Soft Defect Localization (SDL) method has been a common failure analysis technique used in fault isolation of temperature dependent failures, however proper signal conditioning and conversion of the monitored signal into a pass/fail signal are critical in acquiring an accurate defect location. This paper presents case studies where LabVIEW software using NI-PXI test platform was successfully implemented to effectively convert the failure mode into a pass/fail signal which provided a reliable SDL result.

Soft Defect Localization (SDL) is a laser scanning methodology that is commonly used to isolate integrated circuits soft defects. The device is exercised by a functional vector set in a loop manner while localized laser heating stimulates a change in the pass/ fail (P/F) response at the location of the defect or critical path. Although SDL is effective for this purpose, long scan time arising from test overheads, can be a concern to turnaround time for root cause understanding. In this paper, an optimized scheme on synchronous SDL that has a potential to eliminate more than 90% of tester overheads and improve overall SDL test time by at least 17% is proposed. This is achieved by optimizing SDL test loop algorithm.

This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

This presentation is an application-oriented tutorial on laser-assisted device alteration (LADA) and soft defect localization (SDL) techniques and how they are used to analyze marginal digital failures and identify analog circuits that are sensitive to voltage perturbations. The presentation includes well-illustrated instructions for equipment setup and validation, guidelines for collecting and analyzing images, and examples of how to interpret pass/fail sites and assess the effect of laser interactions on circuit behaviors. It also includes a brief overview of time-resolved LADA and introduces the concept of laser-induced fault isolation (LIFA).

Soft defect localization (SDL) is a method of laser scanning microscopy that utilizes the changing pass/fail behavior of an integrated circuit under test and temperature influence. Historically the pass and fail states are evaluated by a tester that leads to long and impracticable measurement times for dynamic random access memories (DRAM). The new method using a high speed comparison device allows SDL image acquisition times of a few minutes and a localization of functional DRAM fails that are caused by defects in the DRAM periphery that has not been possible before. This new method speeds up significantly the turn-around time in the failure analysis (FA) process compared to knowledge based FA.

Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.

This presentation is an application oriented tutorial on laser-assisted device alteration (LADA) and soft defect localization (SDL) techniques and how they are used to analyze marginal digital failures and identify analog circuits that are sensitive to voltage perturbations. The presentation includes well-illustrated instructions for equipment setup and validation, guidelines for collecting and analyzing images, and examples of how to interpret pass/fail sites and assess the effect of laser interactions on circuit behaviors. It also includes a brief overview of time-resolved LADA and introduces the concept of laser-induced fault isolation (LIFA).

Soft Defect Localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across a die.[1,2,3,4] The technique has proven its usefulness for quickly locating failing nodes for functional fails that are temperature, frequency, and/or voltage dependant. The localized heating from the laser can toggle the pass/fail condition as it sweeps over failing nodes with the aforementioned sensitivity. The technique is instrumental in identifying latent defect locations on conditional fails even though they seldom produce light emissions or liquid crystal hot spots. These fails often manifest themselves after reliability stress or at the customer. The technique can also be applied to support design groups with first silicon analysis of timing race conditions and identification of signals that are speed path limiters. The main challenges associated with the technique are in synchronizing the tester with the Laser Scanning Module (LSM) and ensuring the laser can heat the device enough to overcome the pass/fail threshold temperature of the failing node.

This presentation provides an overview of the Arduino microcontroller development board, its features and capabilities, and its integrated design environment. It also provides examples of its use in soft defect localization (SDL) and laser assisted device alteration (LADA).

In the case of conventional planar FET, Dynamic Laser Stimulation (DLS) is a very effective method to isolate marginal failure. Depending on laser sources, DLS is divided by Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). SDL uses 1320nm wavelength laser source in order to induce localized heat. On the other hand, LADA uses 1064nm wavelength laser source to generate photo carriers. But for the FinFET the effect of laser stimulation is not clear yet. This paper introduces the effect of laser stimulation on FinFET transistors based on wavelength, the so called LADA and two-photon LADA. The experimental data show changes in Vth and Idsat with different character for a single FinFET transistor. A case study further explains this laser stimulation effect via scan chain LVcc marginal failure analysis localized with 1320nm CW laser stimulation and nano-probing analysis.

Near-infrared laser stimulation techniques such as OBIRCH, TIVA, OBIC and LIVA are now commonly used to localize resistive defects from the front and backside of ICs. However, these laser stimulation techniques cannot be applied to dynamically failed ICs. Recently, two laser stimulation techniques dedicated to dynamic IC diagnostics have been proposed. These two techniques, called Resistive Interconnection Localization (RIL) and Soft Defect Localization (SDL), combine a continuous laser beam with a dynamically emulated IC. The laser stimulation effect on the circuit is monitored through the applied test pattern pass/fail status. This paper presents the methodology to move from static to dynamic laser stimulation. The application of such Dynamic Laser Stimulation (DLS) techniques is illustrated on dynamically failed microcontrollers.

In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.

Laser-based dynamic analysis has become a very important tool for analyzing advanced process technology and complex circuit design. Thus, many good reference papers discuss high resolution, high sensitivity, and useful applications. However, proper interpretation of the measurement is important as well to understand the failure behavior and find the root cause. This paper demonstrates this importance by describing two insightful case studies with unique observations from laser voltage imaging/laser voltage probing (LVP), optical beam induced resistance change, and soft defect localization (SDL) analysis, which required an in-depth interpretation of the failure analysis (FA) results. The first case is a sawtooth LVP signal induced by a metal short. The second case, a mismatched result between an LVP and SDL analysis, is a good case of unusual LVP data induced by a very sensitive response to laser light. The two cases provide a good reference on how to properly explain FA results.

In this paper, a comprehensive study to find a memory related yield loss in 90 nm technology will be discussed. The loss was related to spacer bridging, blocking silicide formation and Lightly Doped Drain (LDD), source/drain implant. Soft Defect Localization (SDL) techniques [1], sub-micron Atomic Force Microscope (AFM) probing [2] and Time Resolved Emission (TRE) measurements were necessary to obtain an accurate understanding of the problem and the mechanism. Electrical results were compared to simulations. Modified test structures were implemented to monitor the process stability with respect to bridging failures.