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silicon substrate

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Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 92-97, November 14–18, 2010,
...Abstract Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 675-682, November 3–7, 2002,
... silicon wire bonds Characterization of Reactive Ion Etching of Silicon Substrate for Backside Failure Mode Analysis Huixian Wu, James Cargo Agere Systems, IC Quality Organization, Product Analysis Lab Room: 30U-217DJ, 555 Union Blvd., Allentown, PA 18109, USA Phone: 610-712-5998, Email: hwu7@agere.com...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 93-96, November 4–8, 2007,
...Abstract Abstract This paper deals with real-time FTIR (Fourier Transform Infrared Reflectometry) etch depth measurements performed on passive integrated silicon substrates. High-density trench capacitors are non-destructively characterized using an FTIR Michelson type spectrometer. Based...
Proceedings Papers

ISTFA1997, ISTFA 1997: Conference Proceedings from the 23rd International Symposium for Testing and Failure Analysis, 69-78, October 27–31, 1997,
...Abstract Abstract In wafer fabrication (fab), stacking faults (SF) & crystalline defects in the silicon substrate will affect the yield. Wright Etch is the most common chemical etching method used to delineate SF on both (100) & (111) silicon surface. However, when Wright Etch is used...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 197-203, November 6–10, 2016,
...Abstract Abstract Wet Chemical Deprocessing is one of the techniques in exposing embedded structures in an integrated circuit (IC). Layers of the die from the passivation to silicon substrate can be selectively etched using this technique. From series of evaluations conducted, it was discovered...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 246-250, November 5–9, 2017,
... substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 391-396, November 6–10, 2016,
... of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 164-169, November 13–17, 2011,
...Abstract Abstract In this work we present spectrally resolved photon emission microscopy (SPEM) measurements originating from short-channel MOSFETs acquired through the backside of the silicon substrate. Two commonly used detectors have been chosen for the detection of electroluminescence (EL...
Proceedings Papers

ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 121-123, November 12–16, 2000,
...Abstract Abstract Backside failure analysis techniques rely heavily on transmission of near infrared (IR) radiation through the silicon substrate. This statement applies both to emission techniques and active laser probing. Heavy doping of substrates causes them to become highly absorptive...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 179-187, November 11–15, 2001,
... of type and size of packages – from ceramic to exotic plastic molding. They are suited for precise silicon thinning as well as polishing. Finally, the automation and software control of the process offer good reproducibility of chip opening and preparation. For some applications, the silicon substrate...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 389-392, November 11–15, 2001,
... such defects, so backside bulk silicon removal would not be appropriate. Many times when there is a problem with the gate oxide, punch through or pinhole, the size of the hole would be very useful information. Heated KOH is often used to remove poly silicon but it etches so rapidly that the silicon substrate...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 543-551, November 3–7, 2002,
... voltage and current consumption, thus avoiding device or defect degradation upon testing. It is also shown that nonbiased Thermal Laser Stimulation (SEI) tests can localize ESD defects in the silicon substrate. Physical analysis revealed that a thermocouple composed of molten silicon with crystalline...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 121-127, November 6–10, 2005,
... polycrystalline and diffused silicon resistors of 0.18µm technology. The influence of each process parameter on the TLS signal has been observed and evaluated from the front and back side of the circuit. This allowed us to quantify the effect of the silicon substrate thickness on TLS signal detection...
Proceedings Papers

ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 173-176, November 12–16, 2000,
...Abstract Abstract The need for failure analysis from the backside of the die has introduced new challenges in device analysis applications. Standard silicon based detectors are no longer as efficient due to the absorption of emission signals by the silicon substrate, which is now in the optical...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 561-565, October 28–November 1, 2018,
... properties of the dielectric film and its substrate. Modeling shows that sMIM can be used to characterize a range of dielectric film thicknesses spanning both low-k and medium-k dielectric constants. A model system consisting of SiO2 thin films of various thickness on silicon substrates is used to illustrate...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 396-398, November 13–17, 2011,
.... In this paper, we provide a novel backside passive voltage contrast method to improve the failure analysis technique. By thinning down silicon substrate to the active area, a new contact chain from active area is created. Therefore, novel backside PVC is applied to locate the failed site. active voltage...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 155-161, November 3–7, 2002,
...Abstract Abstract Backside imaging through a silicon substrate introduces spherical aberration at high numerical apertures. For a typical 200 micron substrate thickness, these aberrations limit the resolution to less than 1 micron. A theoretical analysis of the aberrations describes...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 186-187, November 6–10, 2016,
... pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 505-509, October 28–November 1, 2018,
... its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 348-350, November 4–8, 2007,
... of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper. dislocations dynamic voltage stress leakage current lightly doped drain p-n junction...