Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

After wafer-die sawing process, sometimes silicon (Si) dust on microchip Al bondpads is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in non-stick on pads (NSOP) problem in assembly process. To eliminate NSOP problem due to Si dust contamination, in this paper, we will study the mechanism of Si dust contamination and propose a concept of Si dust corrosion. A theoretical model will be introduced so as to explain Si dust contamination and corrosion problem during wafer die sawing process. Based on the mechanism proposed, Si dust contamination and corrosion is related to galvanic corrosion as OH- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion, but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads, especially at the pinholes/corrosive areas. Poly-H2SiO3 and Si-Al-O complex compounds are “gel-like” material and stick onto the surface of bondpads. It is insoluble in water and difficult to be cleaned away by DI water during or after wafer die sawing process and will cause bondpad discoloration or/and NSOP problem. Some eliminating methods of Si dust contamination and corrosion on Al bondpads during wafer die sawing process are also discussed.

The ICCDLAB (Integrated Circuit for Characterization and Debug Laboratory) test chip is a full custom silicon chip dedicated to failure analysis. This chip embeds several custom devices designed to highlight, reproduce, and simulate defects, as well as enhance the signatures obtained through failure analysis techniques that are used to locate defects in circuits. The ICCDLAB serves as a versatile tool for failure analysts, providing a “Swiss army knife” and a failure analysts’ playground at the same time. The chip offers a simple means of covering an exhaustive catalog of failure analysis techniques and approaches, allowing for equipment benchmarking, training of individuals new to the failure analysis field, understanding of failure mechanisms and signatures, simulation of defect behaviors, and support for development of new techniques.

The development of modern power semiconductors requires the reduction of the resistance in the on-state of the device. One way to accomplish this is to reduce the bulk silicon thickness. To reach low final Si thicknesses, the grinding processes have to be adapted and optimized and new process-flows, such as dicing before grinding (DBG), must be employed.

Atom probe tomography is used to characterize the 3D Al dopant distribution within the gate diffusion region of a deconstructed SiC n-channel junction field effect transistor. The data reveals extensive inhomogeneities in the dopant distribution, which manifests as large Al clusters - some of which are ring-shaped and indicative of dopant segregation to lattice defects in the SiC. The presence of defects in the SiC is confirmed by transmission electron microscopy of an identical region. Factors that may impact the atom probe data quality and consequently complicate data interpretation are considered, and their severity evaluated. The possible origin of the lattice defects in the SiC and the corresponding implications for device performance and reliability are also discussed. Overall, the utility of atom probe tomography and correlative transmission electron microscopy for revealing potential failure mechanisms of next-generation semiconductor devices is demonstrated.

Laser-based fault injection (LFI) attacks are powerful physical attacks with high precision and controllability. Therefore, attempts have been in the literature to model and simulate the laser effect in pre-silicon digital designs. However, these efforts can only model the laser effect on small SPICE or TCAD circuits of individual standard cells. This paper proposes security properties and a machine-learning assisted layout signoff framework in verifying the full-chip layout's resiliency against LFI. In the framework, we leveraged the commercial SoC power integrity sign-off tool to inject the Gaussian laser current to any spot in the layout, by considering different layout features such as power distribution network, decoupling capacitor placement, metal geometry, instance switching power, etc. To avoid exhaustive analysis of all layout spots regardless of LFI criticality, we use security properties to drive the assessment and identify critical areas. We then use SPICE simulations and machine learning to develop cell-level laser fault models under different laser-induced transient current intensities. This laser cell library is used during full-chip LFI feasibility analysis for the cells inside laser illumination, enabling precise layout -level design fix for critical cells failing the fault injection threshold. Finally, we show the effectiveness of the proposed framework by analyzing the fully implemented AES design layout.

In wafer fabrication, silicon defects on the substrate directly affect the yield of the wafer. In this paper, we will study and discuss a chemical delayering and delineate method for silicon defects in wafer fabrication using Secco etch. It is well-known that during delayering process of wafer, the removal of polysilicon (Poly-Si) layer is very difficult, especially for the wide-layer polysilicon (Poly-Si) which is difficult to completely remove with HF acid solution. We introduce a chemical recipe to fast delayer polysilicon layer completely before delineating silicon defects on silicon substrate using Secco etch. Those skilled in the art could be experiment within half an hour to get analysis results. It saves time and improves operational efficiency. Moreover, based on the experimental results we think that it is possible to identify the root cause according to the shapes of silicon defects using Secco etch.

We report and demonstrate a new methodology for the localization of dielectric breakdown sites in through-silicon via (TSV) structures. We apply a combination of optical beam induced resistance change (OBIRCH) and mechanical/chemical chip deprocessing techniques to localize nm-sized pinhole breakdown sites in a high aspect ratio 3x50 ìm TSV array. Thanks to the wavelength-selective absorption process in silicon, we can extract valuable defect depth localization info from our laser stimulation measurement. After chip deprocessing we inspect and localize the defect site in the dielectric liner using a scanning electron microscope (SEM). We confirm our results and analysis by cross-sectioning a TSV with a focused-ion beam (FIB).

High numerical aperture (NA) laser scanning for fault localization requires the use of special lenses aimed at creating a tightly focused laser spot within an integrated circuit. Typically, extrinsic solid immersion lenses are employed that optimize the refraction at the air-silicon surface. In this feasibility study we investigate with both simulations and experiments the use of integrated diffraction lenses for high-NA imaging. We take the limit to ultrathin silicon and discuss the implications for the lens design and performance.

As advanced silicon-on-insulator (SOI) technology becomes a more widespread technology offering, failure analysis approaches should be adapted to new device structures. We review two nanoprobing case studies of advanced SOI technology, detailing the electrical characterization of a compound gate-to-drain defect as well as the characterization of unexpected SOI source-to-well leakage.

The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is < 5 µm.

In this paper, we present methods for targeted silicon thinning by contour milling to overcome challenges associated with thinning large devices to under 5 µm remaining silicon thickness. Implementation of these techniques are expected to improve the yield of ultra-thin sample preparation and thermal stability of the device through electrical failure analysis for subsequent physical failure analysis. Using a computer numerical controlled milling system, the natural device bow is exploited to thin a specified area of interest by stage tilting before 2D milling. To target a larger area of interests, contour maps are rigged to thin an area preferentially while remaining compatible with existing workflows. Electrical testing have found improved thermal stability of the locally thinned samples over globally thinned samples.

Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.

Stress induced pinholes, cracks, and 'craters' have been found in the gate oxide of a double level metal, single level poly CMOS device containing both analog and digital circuits. These defects have been found randomly across the die in active gate regions, and were found in a line parallel to the gate width. These defects were hidden beneath the polysilicon, and were virtually undetectable electrically. The only electrical indication was a slight shift in the threshold voltage, still within specification limits. The polysilicon had a compressive layer of tungsten silicide (WSi x ) as a cap to lower the polysilicon resistivity and increase circuit speed. It was believed that polysilicon grains or WSi x spikes were migrating into the gate oxide during the WSi x annealing process. The defects were found in unstressed, untested parts, and in parts that passed all tests and stresses. Backside silicon removal showed defects in the gate oxide layer, and subsequent FIB sectioning revealed a WSi x spike. Several techniques were employed to verify the gate oxide defects. Electrical and destructive physical analysis techniques will be presented in the paper.

WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

We describe here the first demonstration of 14nm silicon device characterization using 1.55-2µm emission microscopy as a technique to interrogate the radiative properties of various physical defects. A study is presented and discussed for cases highlighting photo-emission only, hybrid photo-thermal-emission, and thermal-emission only.

The single-bit charge loss of flash memory after stress has been investigated using TEM with selective chemical etching and TCAD simulation for the effect of silicon dopant profile and electrical failure analysis technique. However, the abnormal dopant profile on the drain-side of the failing bit observed in the TEM does not match the leakage behavior from the simulation. A qualitative model for the degradation process is proposed based on the electrical failure analysis results, it is suggested that the hole generated by avalanche breakdown captured by oxide traps on the drain-side during the stress is the source of leakage current.

This paper presents the success story of the learning process by reporting four cases using four different failure analysis techniques. The cases covered are IDDQ leakage, power short, scan chain hard failure, and register soft failure. Hardware involved in the cases discussed are Meridian WS-DP, a wafer-level electrical failure analysis (EFA) system from DCG Systems, V9300 tester from Advantest, and a custom cable interface integrating WSDP and V9300 with the adaption of direct-probe platform that is widely deployed for SoC CP test. Four debug cases are reported in which various EFA techniques are proven powerful and effective, including photon emission, OBIRCH, Thermal Frequency Imaging, LVI, LVP, and dynamic laser stimulation.

In wafer fabrication (fab), stacking faults (SF) & crystalline defects in the silicon substrate will affect the yield. Wright Etch is the most common chemical etching method used to delineate SF on both (100) & (111) silicon surface. However, when Wright Etch is used directly, no SF could be revealed, even if the fab wafers are etched up to 40 mins. The reason is that the fab wafers have thin films deposited on it. After delayering by using dry & wet etches and subsequently Wright Etch, the SF were revealed. But this method is tedious & time consuming as it requires a long time to delayer. Thus in this paper the possibility of using HF (aq) to deprocess fab wafer prior to Wright Etch is investigated. A new chemical etching method - 155 Wright Etch has been proposed. This method has been applied to failure analysis for two years in our FA labs. The analytical results show that it is a rapid & reliable method and is effective in the delineation of SF or crystalline defects on fab silicon wafers due to high temperature oxidation, junction spiking, silicon precipitation, contamination, charging damage, BVGO failure and contact chain failure during fab processes.