This presentation provides an overview of the terminology and concepts associated with semiconductor yield analysis, modeling, and improvement techniques. It compares and contrasts yield models and describes the steps and equipment involved in setting up yield engineering programs targeting specific failures and defects. It also includes case histories showing how different yield analysis models have been used to identify the root cause of random and systematic failures.

This presentation provides an overview of the terminology and concepts associated with semiconductor yield analysis, modeling, and improvement techniques. It compares and contrasts yield models and describes the steps and equipment involved in setting up yield engineering programs targeting specific failures and defects. It also includes case histories showing how different yield analysis models have been used to identify the root cause of random and systematic failures.

Improving semiconductor yield is a multi-dimensional process that must include design, fabrication, and test aspects. Incorporating design-for-manufacturability (DFM) concepts needs to include prior and ongoing learning and experience on what worked and what did not. As feature sizes shrink beyond 130nm, it is possible to identify another class of failures that is more systematic and related not to manufacturing defects but to DFM marginalities related to layout. In this article, it is shown that DFM can also help reduce design sensitivity to process variations. Examples of these failure modes and the lessons learnt are listed: relaxed design rules for repeated patterns, relaxing design rules to reduce yield loss, and special considerations for analog circuit layout.

Bond-pad is an important structure of a microelectronic device because it plays the role of enabling the device to communicate with other external devices. Its integrity directly affects the performance of the microelectronic device. This paper presents our investigation on bond-pad Inter-Metal Dielectric (IMD) crack issue. Our investigation has considered the following factors: top via pattern (sea of vias/without vias) for bond-pad, top metal thickness (8 kÅ /9 kÅ /10 kÅ) and probe overdrive force (30 um/50 um/70 um). The bond-pad IMD cracks were exposed and decorated by chemicals (Aqua Regia and Hydrochloric acid), and inspected by an optical microscope. A scoring system was designed to assess the dependence of the bond-pad IMD crack severity on the above-mentioned factors. The investigation results showed that the IMD crack severity is strongly dependent on the probe overdrive force, top via pattern, and only slightly on top metal thickness.

Presentation slides for the ISTFA 2024 Tutorial session “Yield Basics for Failure Analysts.”

Scan chain integrity yield loss is a common concern, especially in early stage of product yield ramp. Typically, scan chain failure diagnosis can only proceed upon full silicon build and structural test. In this work, we propose a proactive methodology which enables failure debug step to be initiated as early as the onset of device fabrication, to bring forward yield learning. Scan chain cells and nets information are extracted from design data file and converted to inline optical wafer inspection care areas. In this way, the inspection recipe can be optimized for the detection of scan chain related defects. It is shown experimentally that such approach can potentially enhance general defect detection sensitivity by 50% and increase the defect hit probability on scan chain nets. Any findings serve as useful early data for process improvement feedback. Furthermore, marginal defects, which otherwise are not easily revealed using conventional approach, can also be detected to provide early warning for process drifts or variations.

The job of yield and failure analysis (YA and FA) engineers is to identify the root cause of low-yielding wafers. While physical FA is the most definitive method for determining root cause, resource limitations require YA engineers to search for root cause by identifying other wafers with similar yield signatures. The immense number of yield parameters, or features, collected in modern semiconductor processes makes this a difficult task. This paper presents a workflow employing multiple AI techniques to separate groups of wafers by their distinct yield signatures and determine the parameters most important to defining each group. This aids in the disposition of new low-yield wafers, maximizes the learning from previously collected FA wafers, and allows FA resources to be allocated more effectively, prioritizing them for the highest-impact, unknown fail modes.

The Logic Mapper software created by Knights Technology bridges the gap between traditional yield enhancement techniques in the wafer fab and analytical failure techniques in the failure analysis (FA) laboratory. With Logic Mapper, fabs can test logic devices as easily as memory devices. Traditional logic chip yield enhancement techniques within product engineering and wafer fab yield enhancement organizations rely heavily on binsort functional test correlation to anticipate and correct semiconductor process issues. Some of the key shortcomings of these techniques are: · The inability to relate a particular bin’s fallout to a suspect process level. · The inability to distinguish a defect-driven yield issue from a device-integration issue. · The inability to establish a clear link between large populations of failed die. Logic Mapper resolves these key shortcomings by taking the output from functional testers and translating it from a list of failed scan chains into a list of suspected netlist nodes. Using Merlin’s FrameworkTM software, the netlist can be used to identify the X, Y coordinates of a suspected failing node; the failure analysis and yield enhancement engineers have created a starting point for investigating failures. These nodes can then be crossmapped from the circuit design onto the chip’s layout over multiple photomask layers within the design. The ability to translate a logic device’s binsort functional test fail data to defect traces is an advancement in the quality of test information provided for failure analysis and yield enhancement.

With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

The feasibility of the vision of the Semiconductor Industry Association (SIA) Road Maps is rooted in a number of important assumptions. One of them is a requirement of up to 90% yields, which must be achieved for each of the subsequent SIA Road Map milestones. This article argues that such high yields cannot be achieved without a substantial increase in the efficiency of failure analysis. Consequently, it is indicated that testing-based failure analysis is the only alternative which must eventually take over the major responsibility for yield ramping. Finally, it is demonstrated that the increase in the cost of manufacturing due to the increase in failure analysis cost can be justified by extra revenue obtained via faster yield ramping. The article suggests that the testing and IC Design for Diagnosability-based rapid failure analysis are key elements for successful realization of the SIA Road Map objectives.

As semiconductor technology advances from one node to the next, fabrication also becomes increasingly challenging to ramp up production with the most desirable yield and reliable product in a timely manner. At an advanced technology node such as 65nm, the interaction between product design, process margin, and process equipment continues to limit the product yield and reliability performance. Traditional methods, which usually rely on sequential feedback of each experimental lot, require too many learning cycles to achieve target performance, yield, and reliability levels. This paper describes a methodology that potentially accelerates the progression of identifying process and product-design interactions and marginalities during the development stage. It demonstrates the successful application of a failure mode effect analysis design design-of-experiments reticle for extracting process-design interaction information. This approach provides insights to early learning cycles in achieving accelerated critical learning for yield and reliability improvements.

Microscopic imaging and characterization of semiconductor devices and material properties often begin with a sample preparation step. A variety of sample preparation methods such as mechanical lapping and broad ion beam (BIB) milling have been widely used in physical failure analysis (FPA) workflows, allowing internal defects to be analyzed with high-resolution scanning electron microscopy (SEM). However, these traditional methods become less effective for more complicated semiconductor devices, because the cross-sectioning accuracy and reliability do not satisfy the need to inspect nanometer scale structures. Recent trends on multi-chip stacking and heterogenous integration exacerbate the ineffectiveness. Additionally, the surface prepared by these methods are not sufficient for high-resolution imaging, often resulting in distorted sample information. In this work, we report a novel correlative workflow to improve the cross-sectioning accuracy and generate distortion-free surface for SEM analysis. Several semiconductor samples were imaged with 3D X-ray microscopy (XRM) in a non-destructive manner, yielding volumetric data for users to visualize and navigate at submicron accuracy in three dimensions. With the XRM data to serve as 3D maps of true package structures, the possibility to miss or destroy the fault regions is largely eliminated in PFA workflows. In addition to the correlative workflow, we will also demonstrate a proprietary micromachining process which is capable of preparing deformation-free surfaces for SEM analysis.

Hardware obfuscation is a proactive design-for- trust technique against integrated circuit (IC) supply chain threats, i.e., intellectual property (IP) piracy and overproduction. Many studies have evaluated numerous obfuscation techniques, broadly classified as IC camouflaging, logic locking, and split manufacturing. In split manufacturing, threats introduced by an untrusted foundry are eliminated by manufacturing only the front-end of line (FEOL) layers in the high-end untrusted foundry, and back-end of line (BEOL) layers in the design house’s trusted low-end foundry to hide BEOL connections from the untrusted foundry. However, researchers proposed several attacks based on physical layout design heuristic, network-flow model, and placement-routing proximity to extract missing back-end of line connections. Nevertheless, split manufacturing suffers from yield due to challenges in properly aligning FEOL connections with the BEOL. This paper proposes LLE, which protects ICs from piracy and reverse-engineering by untrusted foundries. In this approach, we perform layout-level obfuscation by creating an intermediate metal layer mesh to obscure the BEOL connections from the FEOL. After fabrication from an untrusted foundry, the mesh can be edited using a focused-ion beam (FIB) editing tool in a trusted facility (e.g., FIB lab) to realize the actual inter- connection. Hence, unlike split manufacturing, LLE eliminates the requirement of a separate trusted foundry and establishes trust in the microelectronic supply chain by lowering cost and yield loss. To validate the effectiveness of LLE, we fabricated a test chip in MITLL Low- Power FDSOI CMOS Process. In the silicon test chip, we demonstrate that LLE can prevent IC piracy and reverse engineering with low costs and yield losses in the semiconductor supply chain.

Process defects, either random or systematic, are often the top killers of any semiconductor device. Process defect learning and reduction are the main focuses in both technology development stage and product manufacturing yield ramp stage. In order to achieve fast defect learning, in-line defect inspection is implemented in critical layers during wafer manufacturing. In-line defect inspection is able to detect defects. However, in-line defect inspection alone cannot predict the impact of defects on device functional yield. Failure analysis is an effective method of finding the defects which really cause device functional failures. However, often, the defects found by failure analysis are very different from the original defects, making it difficult to understand the root cause. This paper will describe a methodology how to combine in-line defect inspection and failure analysis together to found the top killer defects and accelerate their root cause identification for fast defect learning and yield improvement.

Listings of the EDFAS 2005-2006 Board of Directors, the ISTFA 2005 Organizing Committee Program Chairs, and other contributors and committee members.

In the automotive IC using thick-film silicon on insulator (SOI) semiconductor device, if the gettering capability of a SOI wafer is inadequate, electrical characteristics degradation by metal contamination arises and the yield falls. At this time, an automotive IC was made experimentally for evaluation of the gettering capability as one of the purposes. In this IC, one of the output characteristics varied from the standard, therefore failure analysis was performed, which found trace metal elements as one of the causes. By making full use of 3D perspective, it is possible to fabricate a site-specific sample into 0.1 micrometre in thickness without missing a failure point that has very minute quantities of contaminant in a semiconductor device. Using energy dispersive X-ray, it is possible to detect trace metal contamination at levels 1E12 atoms per sq cm. that are conventionally detected only by trace element analysis.

Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

In semiconductor manufacturing, the process of laser dicing can result in a loss of yield due to defects associated to the laser interaction with the sample. These defects can be difficult to identify, especially before a proper tuning of the process. Traditional investigation methods, like infrared (IR) inspection and focused-ion beam scanning electron microscopy (FIB-SEM) analysis, are labor-intensive and lack comprehensive insights. Here, we propose a robust correlative microscopy (CM) workflow integrating IR, X-ray Microscopy (XRM), and FIB-SEM tomography analyses, leveraging artificial intelligence (AI) driven algorithm for time- and quality-improved dataset reconstruction, automatic segmentation and defect site identification. Our approach streamlines defect identification, preparation, and characterization. Through AI-enhanced methodologies, as well as femtosecond (fs) laser, we optimize investigation efficiency and extract crucial information about defects properties and evolution. Our research aims to advance semiconductor failure analysis by integrating AI for enhanced defect localization and high-quality 3D dataset acquisition in the realm of laser dicing processes.

Visible to infra-red photon emissions can be readily observed in compound semiconductor devices through the semi-insullating substrate and are useful in fault identification when analyzing yield problems. The techniques described here have uncovered several yield-limiting mechanisms and have lead to rapid and effective corrective measures.

Semiconductor devices are sensitive to contamination that can cause product defects and product rejects. There are many possible types and sources of contamination. Root cause resolution of the contamination source can improve yield. The purpose of contamination troubleshooting is to identify and eliminate major yield limiters. This requires the use of a variety of analytical techniques[1]. Most important, it requires an understanding of the principle of contamination troubleshooting and general knowledge of analytical tests. This paper describes a contamination troubleshooting approach with case studies as examples of its application.