The use of an antireflection coating for backside semiconductor failure analysis is discussed. The process of selecting an appropriate coating is described. Several known coatings are also described in regards to imaging quality, material properties, and the benefits to device analysis applications.

This paper will examine semiconductor wear out at San Onofre Nuclear Generation Station (SONGS). The topics will include case studies, failure mechanisms, diagnostic techniques, failure analysis techniques and root cause corrective actions. Nuclear power plants are unique in that instrumentation and control circuits are continuously energized, are periodically tested, and have been in operation for greater than 25 years. Root cause evaluations at SONGS have identified numerous semiconductor failures due to wear out. Case studies include light output deterioration in opto-isolators, junction alloying failures of transistors and integrated circuits and parametric shifts in operational amplifiers. In most cases the devices do not fail catastrophically but degraded to the point of circuit level functional failure. Failure analysis techniques include circuit analysis, board level troubleshooting to identify the degraded components. Intermittent failures require power cycling, thermal cycling, and long term monitoring to identify the responsible components. Corrective actions for semiconductor wear out at SONGS include enhanced monitoring and proactive change out of identified part types.

Failure analysis of advanced semiconductor devices demands fast and accurate examination from the bulk to the specific area of the defect. Consequently, nanometer resolution and below is critical for finding defects. This work presents the use of argon ion milling methods for multiple length scale sample preparation, micrometer to sub-ångström, without sample preparation- induced artifacts for correlative SEM and TEM failure analysis. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 20 nm are obtained.

Decapsulation of silver wire bonded packages with known techniques often results in damaged silver wires. The chemical properties of silver and silver compounds make silver bond wire inherently susceptible to etching damage by acid, conventional plasma, and oxygen-based Microwave Induced Plasma (MIP). In this paper we solve this problem by developing a specific decapsulation chemistry, based on a hydrogen-containing MIP, for artifact-free decapsulation of silver wire bonded packages.

We present results using near-infrared (NIR) cameras to study emission. characteristics of common defect classes for integrated circuits (ICs). The cameras are based on a liquid nitrogen cooled HgCdTe imaging array with high quantum efficiency and very low read noise. The array was developed for infrared astronomy and has high quantum efficiency in the wavelength range from 0.8 to 2.5 µm. For comparison, the same set of samples used to characterize the performance of the NIR camera were studied using a non-intensified, liquidnitrogen- cooled, slow scan CCD camera (with a spectral range from 400-1100 nm). Our results show that the NIR camera images all of the defect classes studied here with much shorter integration times than the cooled CCD, suggesting that photon emission beyond 1 µm is significantly stronger than at shorter wavelengths.

There are three basic methods used to detect voiding and delamination of die attach materials in semiconductor devices. (1)Electrical measurement of a temperature sensitive parameter (e.g. V be , V gs ) under pulsed power conditions is preferred by manufacturers because the data is easily and quickly obtainable during final electrical test; but electrical measurements are only sensitive to gross voiding or delamination. (2)X-ray analysis produces images which are generally accepted as proof of voiding; but X-ray is completely insensitive to delamination or degradation from thermal stress. (3)Use of Scanning Acoustic Microscopy (SAM) as a non-intrusive analysis tool is increasing in the semiconductor industry and provides accurate evidence of delamination in cases where the other two methods fail. The use of all three methods is recommended to maintain a reliable power product fabrication line at its peak of quality with respect to die attach coverage. This paper will compare and contrast the three methods during thermal shock stress in two manufacturer's power Insulated Gate Bipolar Transistor (IGBT) using a lead-tin solder die attach material.

WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

Transmission electron microscopy (TEM) is now commonly employed in semiconductor device quality control and failure analysis. Precision cross-section specimens (PXTEM) are often required - these are samples that isolate an extremely small volume such as a single failed transistor. PXTEM samples are among the most difficult TEM samples to prepare. It is important for laboratories that perform PXTEM to master a variety of techniques so that the issues of cost, quality, and risk can be properly balanced. This paper addresses these issues while explaining the most common methods of PXTEM preparation along with an illustrative case study.

Bipolar silicon transistors were exposed to Californium (252Cf) radiation and neutron radiation obtained from nuclear facilities. The effect of the radiation on the transistors was measured by recording the transistor's electrical characteristic as a function of radiation fluence. Correlation between Californium (252Cf) -induced and neutron-induced damage and previously published data for proton-induced radiation damage was made. Finally, the effect ofthenna1 annealing on gain recovery was also investigated.

Evaluation of Scanning Electron Microscopes (SEMs) was initiated for the purpose of purchasing a SEM that would improve the productivity of scanning electron microscopy during the cycle of analysis and deprocessing of semiconductor devices in a failure analysis lab. In addition to the need for high image resolution at low electron acceleration voltages, an accurate motorized stage is a major evaluation factor. It is necessary for the analyst to drive directly to a known location such as a memory cell with a high assurance that the site of interest was found. There are two main areas of focus in this paper. First, our SEM evaluation methodology will be presented along with the results of our evaluation. Second, the technology associated with motorized stages will be discussed in light of our requirements for a motorized, highly accurate stage. As a byproduct of this evaluation, this paper is presented so as to push the SEM industry to offer a SEM with an accurate stage for subhalfmicron products at reasonable cost.

When one department performs extensive analysis, the need for common data within a database structure may be required. A realistic paperless database was developed to solve department needs. This database is carried out with the combination of a Client Module, Operation Module and Management Module. The Client Module includes on-line request for analysis, intensive query, retrieval of the analysis result with digital image and image processing. The Operation Module provides real-time digital data acquisition from the analysis equipment, which have the data types of image, text or graph and real-time data transmission to a dedicated server Digital Alpha 4100. The Management Module includes approval of the request for analysis from the Client Module, creation of reports about analysis results and statistical service for the subjects like failure modes in a device, operation time of equipment and so on. These modules allow multi-users to access the database through the Web on the Intranet. Our database can be also linked to the in-line database and the failure analysis with DRT SEM and physical analysis can become more effective with the use of in-line inspection data. This paper presents the framework of the database along with a technical description of the database implementation.

The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Electron-beam induced radiation damage can give rise to large structural collapse and deformation of low k and ultra low k IMD in semiconductor devices, posing great challenges for failure analysis by electron microscopes. Such radiation damage has been frequently observed during both sample preparation by dual-beam FIB and TEM imaging. To minimize radiation damage, in this work we performed systematic studies on every possible failure analysis step that could introduce radiation damage, i.e., pre-FIB sample preparation, FIB milling, and TEM imaging. Based on these studies, we utilized comprehensive technical solutions to radiation damage by each failure analysis step, i.e., low-dose/low-kV FIB and low-dose TEM techniques. We propose and utilize the low-dose TEM imaging techniques on conventional TEM tools without using low-dose imaging control interface/software. With these new methodologies or techniques, the electron-beam induced radiation damage to ultra low k IMD has been successfully minimized, and the combination of single-beam FIB milling and low-dose TEM imaging techniques can reduce structure collapse and shrinkage to almost zero.

A three dimensional (3-D) photon emission failure analysis method has been developed to pinpoint failure sites or emission sites on the x, y, and z planes of a degraded diode. The 3-D analysis consists of a cross-sectioning step process on two adjacent sides of a diode utilizing two photon emission sites from respective sides of the die as a map. This process negates the uncertainty and long processing times during cross-sectional analysis to find minute defects in diodes.

Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.

Subsurface wiring level anomalies in VLSI semiconductor devices are extremely difficult, if not impossible to analyze without de-processing the device to expose suspect wiring. Magnetic Force Microscopy (MFM) is a scanning probe technique that requires minimal sample preparation and has the capability to sense magnetic fields in proximity to thin film conductors with high lateral resolution [1]. In this study, multiple VLSI device conductors were intentionally modified and then the magnetic field around the energized conductors was analyzed using MFM. An overview of the technique and results of the magnetic field analysis are discussed.

This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

In this paper, we carried out PIND (Particle Impact Noise Detection) test and X-ray inspection of a transistor in a TO-18 package for commercial and industrial applications. From our evaluation results, we explain the validity of the PIND test by comparing PIND test and X-ray inspection results. We make clear that PIND test is able to detect internal foreign material that may be transparent to X-ray inspection. In addition, we report analysis results of internal foreign materials from defective devices. This matter suggests that a problem is contamination control in the manufacturing process, most likely the sealing process.

Physical characterization of individual process steps and their interaction with other processes is a key element during development as well as manufacturing of semiconductor technology. This paper presents a number of examples that illustrate the usefulness of the combination of sample wet-chemical staining techniques with the latest generation SEM imaging capabilities. The examples show how sample preparation and imaging conditions have to be tailored to the specific needs. The combination of application-tailored chemical decoration with high-resolution material contrast SEM imaging has proven to be a powerful technique for the characterization of manufacturing process steps. Only with the novel imaging modes available in the latest generation SEM instruments, it became possible to perform investigations with fast turnaround times and on large sample areas.

Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.