During the activity in the Failure Analysis (FA) laboratory, all corresponding findings and conclusions are included in a series of documents known as the FA reports. They shall, in the first place, inform the requestor about the analysis results. But additionally, they shall provide information to solve similar cases. Therefore, these documents play a key role in preserving the knowledge acquired by the engineers as they become available for consultation during future works. The different information systems in FA consist of databases, file shares, wikis, or other human-readable forms. However, the heterogeneity of these databases and the large number of independent documents make it inefficient for manual consultation. In this context, this paper proposes an application of Natural Language Processing (NLP) known as Named Entity Recognition (NER), consisting of an AI-based detection of key concepts in textual data in the form of annotations. These annotations can then be used to boost search systems or other AI models.

Insulated Gate Bipolar Transistors (IGBT) and silicon carbide (SiC) based MOSFETs have become the predominantly used power semiconductors in particular in automotive applications. For failure analysis of such devices, site-specific access to subsurface fault sites is required, as is understanding their construction and junction profiles, and how the device turns on. We have applied focused ion beam-scanning electron microscopy (FIB-SEM) tomography to visualize inner structure and dopant distributions of an IGBT and of a SiC MOSFET in three dimensions (3D). Such 3D data can be used to complement 2D electron beam induced current (EBIC) measurements obtained at site-specific FIB cross-sections in these devices.

Presentation slides for the ISTFA 2023 Tutorial session “Sample Preparation for Electron Microscopy Characterization (SEM and TEM) and Failure Analysis of Advanced Semiconductor Devices.”

Presentation slides for the ISTFA 2023 Tutorial session “TEM Techniques for Semiconductor Failure Analysis.”

Presentation slides for the ISTFA 2023 Tutorial session “Power Semiconductor Failure Analysis Tutorial.”

Failure Analysis (FA) is a complex activity that requires careful and complete documentation of all findings and conclusions to preserve knowledge acquired by engineers in this process. Modern FA systems store this data in text or image formats and organize it in databases, file shares, wikis, or other human-readable forms. Given a large volume of generated FA data, navigating it or searching for particular information is hard since machines cannot process the stored knowledge automatically and require much interaction with experts. In this paper, we investigate applications of modern Natural Language Processing (NLP) approaches to the classification of FA texts with respect to electrical and/or physical failures they describe. In particular, we study the efficiency of pretrained Language Models (LM) in the semiconductors domain for text classification with deep neural networks. Evaluation results of LMs show that their vocabulary is not suitable for FA applications, and the best classification accuracy of appr. 60% and 70% for physical and electrical failures, respectively, can only be reached with fine-tuning techniques.

This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

High-power, diode pump laser modules with improved 0.25% antireflective (AR) coating exhibited low (weak) or zero (dead) power emitters after 1000+ hours life-test. Catastrophic optical mirror damage (COMD) was suspected due to a facet coating upgrade but was not physically observed. Electroluminescence ‘fingerprinting’ lent to a contradictory catastrophic bulk damage (COBD) failure mechanism. The Customer wished to clearly understand how an AR coating change caused COBD and not COMD. This paper emphasizes how the astute failure analyst must remain a ‘conscious observer’ deploying concerted analysis steps to truly unmask root-cause amidst conflicted stakeholders.

We describe a fully integrated solution for millimeter-scale delayering of both logic and memory semiconductor devices. The flatness of the delayered device is controlled by an artificial intelligence algorithm, which uses feedback from multiple analytical detectors to control milling parameter adjustments in real time. The result is the precise removal of device layers and a highly planar surface.

Failure analysis of advanced semiconductor devices demands fast and accurate examination from the bulk to the specific area of the defect. Consequently, nanometer resolution and below is critical for finding defects. This work presents the use of argon ion milling methods for multiple length scale sample preparation, micrometer to sub-ångström, without sample preparation- induced artifacts for correlative SEM and TEM failure analysis. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 20 nm are obtained.

Decapsulation of silver wire bonded packages with known techniques often results in damaged silver wires. The chemical properties of silver and silver compounds make silver bond wire inherently susceptible to etching damage by acid, conventional plasma, and oxygen-based Microwave Induced Plasma (MIP). In this paper we solve this problem by developing a specific decapsulation chemistry, based on a hydrogen-containing MIP, for artifact-free decapsulation of silver wire bonded packages.

We present results using near-infrared (NIR) cameras to study emission. characteristics of common defect classes for integrated circuits (ICs). The cameras are based on a liquid nitrogen cooled HgCdTe imaging array with high quantum efficiency and very low read noise. The array was developed for infrared astronomy and has high quantum efficiency in the wavelength range from 0.8 to 2.5 µm. For comparison, the same set of samples used to characterize the performance of the NIR camera were studied using a non-intensified, liquidnitrogen- cooled, slow scan CCD camera (with a spectral range from 400-1100 nm). Our results show that the NIR camera images all of the defect classes studied here with much shorter integration times than the cooled CCD, suggesting that photon emission beyond 1 µm is significantly stronger than at shorter wavelengths.

There are three basic methods used to detect voiding and delamination of die attach materials in semiconductor devices. (1)Electrical measurement of a temperature sensitive parameter (e.g. V be , V gs ) under pulsed power conditions is preferred by manufacturers because the data is easily and quickly obtainable during final electrical test; but electrical measurements are only sensitive to gross voiding or delamination. (2)X-ray analysis produces images which are generally accepted as proof of voiding; but X-ray is completely insensitive to delamination or degradation from thermal stress. (3)Use of Scanning Acoustic Microscopy (SAM) as a non-intrusive analysis tool is increasing in the semiconductor industry and provides accurate evidence of delamination in cases where the other two methods fail. The use of all three methods is recommended to maintain a reliable power product fabrication line at its peak of quality with respect to die attach coverage. This paper will compare and contrast the three methods during thermal shock stress in two manufacturer's power Insulated Gate Bipolar Transistor (IGBT) using a lead-tin solder die attach material.

WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

Physical characterization of individual process steps and their interaction with other processes is a key element during development as well as manufacturing of semiconductor technology. This paper presents a number of examples that illustrate the usefulness of the combination of sample wet-chemical staining techniques with the latest generation SEM imaging capabilities. The examples show how sample preparation and imaging conditions have to be tailored to the specific needs. The combination of application-tailored chemical decoration with high-resolution material contrast SEM imaging has proven to be a powerful technique for the characterization of manufacturing process steps. Only with the novel imaging modes available in the latest generation SEM instruments, it became possible to perform investigations with fast turnaround times and on large sample areas.

Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.

Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.

Transmission electron microscopy (TEM) is now commonly employed in semiconductor device quality control and failure analysis. Precision cross-section specimens (PXTEM) are often required - these are samples that isolate an extremely small volume such as a single failed transistor. PXTEM samples are among the most difficult TEM samples to prepare. It is important for laboratories that perform PXTEM to master a variety of techniques so that the issues of cost, quality, and risk can be properly balanced. This paper addresses these issues while explaining the most common methods of PXTEM preparation along with an illustrative case study.

Bipolar silicon transistors were exposed to Californium (252Cf) radiation and neutron radiation obtained from nuclear facilities. The effect of the radiation on the transistors was measured by recording the transistor's electrical characteristic as a function of radiation fluence. Correlation between Californium (252Cf) -induced and neutron-induced damage and previously published data for proton-induced radiation damage was made. Finally, the effect ofthenna1 annealing on gain recovery was also investigated.

Evaluation of Scanning Electron Microscopes (SEMs) was initiated for the purpose of purchasing a SEM that would improve the productivity of scanning electron microscopy during the cycle of analysis and deprocessing of semiconductor devices in a failure analysis lab. In addition to the need for high image resolution at low electron acceleration voltages, an accurate motorized stage is a major evaluation factor. It is necessary for the analyst to drive directly to a known location such as a memory cell with a high assurance that the site of interest was found. There are two main areas of focus in this paper. First, our SEM evaluation methodology will be presented along with the results of our evaluation. Second, the technology associated with motorized stages will be discussed in light of our requirements for a motorized, highly accurate stage. As a byproduct of this evaluation, this paper is presented so as to push the SEM industry to offer a SEM with an accurate stage for subhalfmicron products at reasonable cost.