Abstract In this paper, we describe automated FIB for TEM sample preparation using iFast software on a Helios 450HP dual-beam system. A robust iFast automation recipe needs to consider as many variables as possible in order to ensure consistent sample quality and high success rate. Variations mainly come from samples of different materials, structures, surface patterns, surface topography and surface charging. The recipe also needs to be user-friendly and provide high flexibility by allowing users to choose preferable working parameters for specific types of samples, such as: grounding, protective layer coating, milling steps, and final TEM lamella thickness/width. In addition to the iFast recipe, other practical factors affecting automation success rate are also discussed and highlighted.

Abstract Scanning microwave impedance microscopy was used to analyze a CMOS image sensor sample to reveal details of the dopant profiling in planar and cross-sectional samples. Sitespecific capacitance-voltage spectroscopy was performed on different regions of the samples.

Abstract The advances on IC technology have made defect localization extremely challenging. “Soft” failures (resistive vias and contacts) are typically difficult to localize using commonly available failure analysis (FA) techniques such as emission microscopy (EMMI) and scanning optical microscopy (SOM), and often cannot be observed by two-dimensional inspections using layer by layer removal. The article describes the Resistive Contrast Imaging (RCI) defect localization technique (also known as Electron Beam Absorbed Current (EBAC), instrumentations, and case studies on test structures or process control monitors especially designed to detect “soft” open failures on advanced (28nm and below) technology devices. It also lists the key SEM parameters critical for effective FA using the RCI nano-probing system.

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Abstract The use of an antireflection coating for backside semiconductor failure analysis is discussed. The process of selecting an appropriate coating is described. Several known coatings are also described in regards to imaging quality, material properties, and the benefits to device analysis applications.

Abstract This paper will examine semiconductor wear out at San Onofre Nuclear Generation Station (SONGS). The topics will include case studies, failure mechanisms, diagnostic techniques, failure analysis techniques and root cause corrective actions. Nuclear power plants are unique in that instrumentation and control circuits are continuously energized, are periodically tested, and have been in operation for greater than 25 years. Root cause evaluations at SONGS have identified numerous semiconductor failures due to wear out. Case studies include light output deterioration in opto-isolators, junction alloying failures of transistors and integrated circuits and parametric shifts in operational amplifiers. In most cases the devices do not fail catastrophically but degraded to the point of circuit level functional failure. Failure analysis techniques include circuit analysis, board level troubleshooting to identify the degraded components. Intermittent failures require power cycling, thermal cycling, and long term monitoring to identify the responsible components. Corrective actions for semiconductor wear out at SONGS include enhanced monitoring and proactive change out of identified part types.

Abstract Decapsulation of silver wire bonded packages with known techniques often results in damaged silver wires. The chemical properties of silver and silver compounds make silver bond wire inherently susceptible to etching damage by acid, conventional plasma, and oxygen-based Microwave Induced Plasma (MIP). In this paper we solve this problem by developing a specific decapsulation chemistry, based on a hydrogen-containing MIP, for artifact-free decapsulation of silver wire bonded packages.

Abstract We present results using near-infrared (NIR) cameras to study emission. characteristics of common defect classes for integrated circuits (ICs). The cameras are based on a liquid nitrogen cooled HgCdTe imaging array with high quantum efficiency and very low read noise. The array was developed for infrared astronomy and has high quantum efficiency in the wavelength range from 0.8 to 2.5 µm. For comparison, the same set of samples used to characterize the performance of the NIR camera were studied using a non-intensified, liquidnitrogen- cooled, slow scan CCD camera (with a spectral range from 400-1100 nm). Our results show that the NIR camera images all of the defect classes studied here with much shorter integration times than the cooled CCD, suggesting that photon emission beyond 1 µm is significantly stronger than at shorter wavelengths.

Abstract There are three basic methods used to detect voiding and delamination of die attach materials in semiconductor devices. (1)Electrical measurement of a temperature sensitive parameter (e.g. V be , V gs ) under pulsed power conditions is preferred by manufacturers because the data is easily and quickly obtainable during final electrical test; but electrical measurements are only sensitive to gross voiding or delamination. (2)X-ray analysis produces images which are generally accepted as proof of voiding; but X-ray is completely insensitive to delamination or degradation from thermal stress. (3)Use of Scanning Acoustic Microscopy (SAM) as a non-intrusive analysis tool is increasing in the semiconductor industry and provides accurate evidence of delamination in cases where the other two methods fail. The use of all three methods is recommended to maintain a reliable power product fabrication line at its peak of quality with respect to die attach coverage. This paper will compare and contrast the three methods during thermal shock stress in two manufacturer's power Insulated Gate Bipolar Transistor (IGBT) using a lead-tin solder die attach material.

Abstract WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

Abstract Transmission electron microscopy (TEM) is now commonly employed in semiconductor device quality control and failure analysis. Precision cross-section specimens (PXTEM) are often required - these are samples that isolate an extremely small volume such as a single failed transistor. PXTEM samples are among the most difficult TEM samples to prepare. It is important for laboratories that perform PXTEM to master a variety of techniques so that the issues of cost, quality, and risk can be properly balanced. This paper addresses these issues while explaining the most common methods of PXTEM preparation along with an illustrative case study.

Abstract Bipolar silicon transistors were exposed to Californium (252Cf) radiation and neutron radiation obtained from nuclear facilities. The effect of the radiation on the transistors was measured by recording the transistor's electrical characteristic as a function of radiation fluence. Correlation between Californium (252Cf) -induced and neutron-induced damage and previously published data for proton-induced radiation damage was made. Finally, the effect ofthenna1 annealing on gain recovery was also investigated.

Abstract Evaluation of Scanning Electron Microscopes (SEMs) was initiated for the purpose of purchasing a SEM that would improve the productivity of scanning electron microscopy during the cycle of analysis and deprocessing of semiconductor devices in a failure analysis lab. In addition to the need for high image resolution at low electron acceleration voltages, an accurate motorized stage is a major evaluation factor. It is necessary for the analyst to drive directly to a known location such as a memory cell with a high assurance that the site of interest was found. There are two main areas of focus in this paper. First, our SEM evaluation methodology will be presented along with the results of our evaluation. Second, the technology associated with motorized stages will be discussed in light of our requirements for a motorized, highly accurate stage. As a byproduct of this evaluation, this paper is presented so as to push the SEM industry to offer a SEM with an accurate stage for subhalfmicron products at reasonable cost.

Abstract In their daily work, engineers in the Failure Analysis (FA) laboratory generate numerous documents reporting all their tasks, findings, and conclusions regarding every device they are handled. This data stores valuable knowledge for the laboratory that other experts can consult, however, the nature of it, as individual reports reporting concrete devices and their corresponding processes, makes it inefficient to consult for the human experts. In this context, the following paper proposes a Artificial Intelligence solution for the gathering of this FA knowledge stored in the numerous documents generated in the laboratory. Therefore, we have generated a dataset of FA reports along with their corresponding electrical signatures and physical failures in order to train different supervised classifiers. The results show that the models are able of capturing the patterns underlying the different jobs and predict the causes, showing slightly better results for the physical hypotheses.

Abstract Considering the growing need for the use of semiconductors in the automotive industry, this paper aims to describe the analyzing process from an automotive manufacturer point of view. The use of X-Ray Microscopy and a combination of ToF-SIMS and FIB are shown.

Abstract In this work we present a large-volume workflow for fast failure analysis of microelectronic devices that combines a stand-alone ps-laser ablation tool with a SEM/Xe Plasma FIB system. In this synergy, the ps-laser is used to quickly remove large volumes of bulk material while the SEM/Xe Plasma FIB is used for precise end-pointing to the feature of interest and fine surface polishing after laser. The concept of having a stand-alone laser tool obeys the logic of maximizing productivity as both systems can work simultaneously and continuously. As application examples we first present a full workflow to prepare an artefact-free, delamination-free cross-section in an AMOLED mobile display. We also present applications examples that require cm-sized long cuts to cut through whole microelectronic devices, or removal of cubic-mm of material to prepare mm-sized cross-sections in packages. We discuss a way how to implement correlation data across the laser and FIBSEM platforms through SYNOPSYS Avalon SW allowing precise navigation to the area of interest using layout circuit overlays. We also show an example of image bitmap overlay to navigate across platforms and end-pointing.

Abstract This paper presents a development in semiconductor device delayering by broad ion beam milling that offers a uniform delayering area on a millimeter scale. A milling area of this size is made possible by the user's ability to position ion beams individually to cover the desired area. This flexibility in ion beam positioning also enables more precise targeting of an area of interest.

Abstract Physical characterization of individual process steps and their interaction with other processes is a key element during development as well as manufacturing of semiconductor technology. This paper presents a number of examples that illustrate the usefulness of the combination of sample wet-chemical staining techniques with the latest generation SEM imaging capabilities. The examples show how sample preparation and imaging conditions have to be tailored to the specific needs. The combination of application-tailored chemical decoration with high-resolution material contrast SEM imaging has proven to be a powerful technique for the characterization of manufacturing process steps. Only with the novel imaging modes available in the latest generation SEM instruments, it became possible to perform investigations with fast turnaround times and on large sample areas.

Abstract Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.

Abstract Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.