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Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 405-409, November 10–14, 2019,
... Nickel Flakes: Past, Present and Future Ken Turner, Kevin Polito Hi-Rel Laboratories, Spokane, WA USA April, 2019 Abstract Pure nickel lidded TO style packages are a common packaging type for active microelectronics with application in various fields including commercial, aerospace and defense...
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Pure nickel lidded TO style packages are a common packaging type for active microelectronics with application in various fields including commercial, aerospace and defense. This paper will focus on the history of nickel flakes in the industry, current trends and failure analysis findings, and future considerations for this potential failure mechanism. In 2004 Hi-Rel Laboratories became involved in an important nickel flake study which led to further inspections to document and evaluate nickel flakes in TO style lids from various customers and manufacturers. Through 2015 these inspections also assisted manufacturers to evaluate the effectiveness of their lid preparation and various cleaning methods for this package style, resulting in a substantial reduction in total number of nickel flakes greater than the specified critical dimension. In 2019 investigations were rekindled after the discovery of a suspected nickel flake-induced failure in transistors from a manufacturer not involved in prior analyses. As part of the investigation, which included nickel flake inspection of 38 total transistors from 1992, 2010, 2011 and 2017 lot date codes, the components were subjected to various environmental conditions including vibration, mechanical shock, mild thermal cycling, ionized airflow and degaussing. It was discovered that degaussing alone greatly affected the adhesion of the nickel flakes to the internal surfaces, causing the majority of the flakes to break free. The methodology, findings and implications of this analysis will be discussed.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 11-13, November 11–15, 2001,
... X-ray tomography X-Ray Tomography of Integrated Circuit Interconnects: Past and Future Zachary H. Levine and Steven Grantham National Institute of Standards and Technology, Gaithersburg, MD 20899-8410 Abstract A scanning transmission x-ray microscope was used to perform x-ray tomography...
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A scanning transmission x-ray microscope was used to perform x-ray tomography of integrated circuit interconnects. Reconstructions of test circuits were made with 140 nm 3D resolution in the best case.
Proceedings Papers
ISTFA2024, ISTFA 2024: Tutorial Presentations from the 50th International Symposium for Testing and Failure Analysis, i1-i57, October 28–November 1, 2024,
... Abstract Presentation slides for the ISTFA 2024 Tutorial session “Electron-Beam Probing of Modern Integrated Circuits: Moving Forward while Borrowing from the Past.” electron-beam probing integrated circuits httpsdoi.org/ 10.31339/asm.cp.istfa2024tpi1 RIDING THE WAVE OF ARTIFICIAL...
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Presentation slides for the ISTFA 2024 Tutorial session “Electron-Beam Probing of Modern Integrated Circuits: Moving Forward while Borrowing from the Past.”
Proceedings Papers
ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 439-444, November 3–7, 2002,
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High optical power is considered as the source of failures in passive optical elements. Optical connectors, in particular, have been studied because of the unavoidable exposure of their optical interfaces to environmental issues during insertion and extraction. Cleaning and insertion/extraction procedures are investigated. Evidence for burn-out, depending on the different procedures, calls for new suitable rules for handling during equipment operation and testing.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 177-178, November 1–5, 2015,
... Abstract The entire electronics industry is now facing a much more insidious counterfeit threat than at any time in the past. The existence of cloned electronic components bearing the markings of major component manufacturers in today’s global supply chains has been clearly established within...
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The entire electronics industry is now facing a much more insidious counterfeit threat than at any time in the past. The existence of cloned electronic components bearing the markings of major component manufacturers in today’s global supply chains has been clearly established within SMT’s labs over the past 3 years. The most worrisome aspect of these “made from scratch” fakes is their ability to easily pass current Industry-Standard counterfeit inspection processes and electrical testing to the manufacturers’ data sheet. My presentation will focus on several actual examples of this most concerning advanced counterfeiter capability and some of the processes utilized by SMT as an obsolescence component supplier and testing lab to mitigate this new and growing threat from making it to our OEM & CM customers.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 248-255, November 13–17, 2011,
... Abstract IC packages have been greatly improved over the past several years. With the adoption of Cu wires and new green EMC (Epoxy Molding Compound), the suppression of lead, the use of Cu pillars and the increased number of dies, the verification of the quality of the assembly and failure...
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IC packages have been greatly improved over the past several years. With the adoption of Cu wires and new green EMC (Epoxy Molding Compound), the suppression of lead, the use of Cu pillars and the increased number of dies, the verification of the quality of the assembly and failure analysis becomes critical. Starting twelve years ago, LASER ablation was introduced as a means to facilitate the pre-decapsulation of packages aiming at a completion by wet chemistry (acids) or dry chemistry (plasma). The decapsulation process with acid at medium temperature (75°C) does not permit to keep the Cu wires intact. Our studies and work in the past several years has consisted in lowering the temperature of acid use in order to minimize the effect of acid attack on the Al pads and Cu wires. Currently the thinnest wires used are 0.6 mil in diameter (approximately 15 μm). In this article we will demonstrate that decapsulations at sub-ambient temperatures are now possible and give expected results. Moreover, openings at near ambient temperature reduce the component deformation and also the deformation of its constituents compared to decapsulations at medium or high temperature.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 392-395, October 30–November 3, 2022,
... Abstract Copper (Cu) material was extensively studied in the past years and widely implemented in high volume wire bonding process as a replacement of Gold (Au) material during semiconductor device fabrication. No doubt, Cu wire provide low cost alternative to gold with higher thermal...
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Copper (Cu) material was extensively studied in the past years and widely implemented in high volume wire bonding process as a replacement of Gold (Au) material during semiconductor device fabrication. No doubt, Cu wire provide low cost alternative to gold with higher thermal and electrical conductivity, but it does pose some drawback especially after reliability stress. One of the most common problem was ball lifted after component gone through several reliability stress tests. In this paper, several FA analytical techniques and procedures will be discussed in detail to demonstrate the use of these techniques in ball lifting investigation.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 123-129, November 10–14, 2019,
... Abstract With the development of semiconductor technology and the increment quantity of metal layers in past few years, backside EFA (Electrical Failure Analysis) technology has become the dominant method. In this paper, abnormally high Signal Noise Ratio (SNR) signal captured by Electro...
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With the development of semiconductor technology and the increment quantity of metal layers in past few years, backside EFA (Electrical Failure Analysis) technology has become the dominant method. In this paper, abnormally high Signal Noise Ratio (SNR) signal captured by Electro-Optical Probing (EOP)/Laser Voltage Probing (LVP) from backside is shown and the cause of these phenomena are studied. Based on the real case collection, two kinds of failure mode are summarized, and simulated experiments are performed. The results indicate that when a current path from power to ground is formed, the high SNR signal can be captured at the transistor which was on this current path. It is helpful of this consequence for FA to identify the failure mode by high SNR signal.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 227-231, November 10–14, 2019,
... Abstract The development of vertical 3D NAND technology over the past 5 years has been accelerated by the parallel development of metrology techniques capable of characterizing these device stacks. Current trends point toward a continuous scaling of dimensions along the z-axis, involving...
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The development of vertical 3D NAND technology over the past 5 years has been accelerated by the parallel development of metrology techniques capable of characterizing these device stacks. Current trends point toward a continuous scaling of dimensions along the z-axis, involving a critical etch step with aspect ratios of ~50:1. These high aspect ratio process steps present both fabrication and metrology challenges where the channel holes can bend, bow, and pinch off throughout the stack. Work presented herein demonstrates the capability of an automated workflow developed using the Thermo Scientific™ Helios™ G4 HXe DualBeam™ platform. The workflow iteratively exposes desired layers within the NAND stack, collects high resolution SEM images, and performs metrology to enable statistical analysis of trends as a function of depth within the stack. Results will be presented from 3 sites in an automatically delayered 72-layer 3D NAND die. Automated SEM metrology was performed every 10 layers, capturing more than 6000 devices. Over 19000 measurements were made on imaged devices yielding assessment of statistically significant trends in the planar cell area, eccentricity, and position of the bits as a function of depth.
Proceedings Papers
ISTFA1996, ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis, 351-355, November 18–22, 1996,
... Abstract A wealth of literature has arisen in the past couple of decades regarding the phenomenon of electromigration. In addition, stress voiding has received considerable attention from the research community. Some of the work on the structural character of these phenomena has focussed...
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A wealth of literature has arisen in the past couple of decades regarding the phenomenon of electromigration. In addition, stress voiding has received considerable attention from the research community. Some of the work on the structural character of these phenomena has focussed on the roles of crystallographic texture and grain boundary structure. It is an experimental fact that the strength of the (111) fiber texture is an indication of interconnect reliability, the stronger the texture, the more reliable the interconnect. It is also presumed that grain boundary diffusivity is a controlling factor in electromigration behavior of polycrystalline lines. Undesirable grain boundary structure is likely a cause of failure in lines with a bamboo structure as well because they are often sites of stress concentration and local incompatibilities. The present study focuses upon electromigration failures in test structures of Al-Cu lines and stress voiding in Cu lines. Texture and grain boundary structure were measured directly on the specimens using electron back-scatter diffraction and orientation imaging. It is observed that a correlation exists between grain boundary structure and void formation in strongly textured polycrystalline lines. Results indicate that secondary orientation (not just the (111) fiber), and boundary structure may be of primary importance in optimizing interconnect microstructure.
Proceedings Papers
ISTFA1997, ISTFA 1997: Conference Proceedings from the 23rd International Symposium for Testing and Failure Analysis, 41-49, October 27–31, 1997,
... and a flood beam fluorescence pump source, usually an ultraviolet arc lamp. Interest in FMI has grown greatly over the past few years [3-9] due largely to its unique combination of high spatial and thermal resolution. In this paper, we demonstrate that the existing infrastructure found on a scanning laser...
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We have developed scanning fluorescent microthermal imaging (SFMI), a new failure analysis technique. The fluorescent microthermal imaging (FMI) technique has been used for over a decade in its original form [1-2]. FMI normally relies on the use of a cooled, slow-scan CCD camera and a flood beam fluorescence pump source, usually an ultraviolet arc lamp. Interest in FMI has grown greatly over the past few years [3-9] due largely to its unique combination of high spatial and thermal resolution. In this paper, we demonstrate that the existing infrastructure found on a scanning laser microscope (SLM) is capable of acquiring the necessary images for SFMI using its scanned laser source and a point detector. The implications ofthis work are significant in that now high spatial and thermal resolution images can be made using an SLM without the need of additional, expensive hardware.
Proceedings Papers
ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 57-66, November 15–19, 1998,
... voltage waveform. Small pads produced by FIB have small acceptable impact on the stress waveform of the circuit and they still allow accurate measurement of the internal device nodes. FIB’s ‘cut and paste’ technique is used to form these probe pads. Some suggestions are made for the proper FIB work...
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Focused Ion Beam (FIB) is used to modify a ring-oscillator circuit to enable the direct characterization of AC hot-carrier effects. Probe access to internal device nodes is necessary to find out the amount of individual device degradation resulting from AC hot-carrier stress. The circuit modification on an existing wafer by FIB enables the direct measurement of individual device in the circuit before and after AC hotcarrier stressing without resorting to new mask sets and silicon wafer processing for new hotcarrier reliability test circuits that can provide realistic stress voltage waveform. Small pads produced by FIB have small acceptable impact on the stress waveform of the circuit and they still allow accurate measurement of the internal device nodes. FIB’s ‘cut and paste’ technique is used to form these probe pads. Some suggestions are made for the proper FIB work in this paper. The results of AC hot-carrier tests with the circuit modified by FIB are also presented with some illustrative figures.
Proceedings Papers
ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 235-244, November 15–19, 1998,
... Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply...
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Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.
Proceedings Papers
ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 323-327, November 15–19, 1998,
... Abstract The growth of the Internet over the past four years provides the failure analyst with a new media for communicating his results. The new digital media offers significant advantages over analog publication of results. Digital production, distribution and storage of failure analysis...
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The growth of the Internet over the past four years provides the failure analyst with a new media for communicating his results. The new digital media offers significant advantages over analog publication of results. Digital production, distribution and storage of failure analysis results reduces copying costs and paper storage, and enhances the ability to search through old analyses. When published digitally, results reach the customer within minutes of finishing the report. Furthermore, images on the computer screen can be of significantly higher quality than images reproduced on paper. The advantages of the digital medium come at a price, however. Research has shown that employees can become less productive when replacing their analog methodologies with digital methodologies. Today's feature-filled software encourages "futzing," one cause of the productivity reduction. In addition, the quality of the images and ability to search the text can be compromised if the software or the analyst does not understand this digital medium. This paper describes a system that offers complete digital production, distribution and storage of failure analysis reports on the Internet. By design, this system reduces the futzing factor, enhances the ability to search the reports, and optimizes images for display on computer monitors. Because photographic images are so important to failure analysis, some digital image optimization theory is reviewed.
Proceedings Papers
ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 463-467, November 12–16, 2000,
... process, we must first properly and accurately quantify and characterize the dicing process. This paper describes the methodology to perform this first step in a premier fashion. In the past, quantification of the dicing process has been a manual operation usually under a microscope. Now there is a new...
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Die cracking is one of the primary failure areas in semiconductor manufacturing and in product longevity. Often die cracking emanates from stress concentrations formed on chips during the dicing process. In order to properly characterize and analyze die cracking relating to the dicing process, we must first properly and accurately quantify and characterize the dicing process. This paper describes the methodology to perform this first step in a premier fashion. In the past, quantification of the dicing process has been a manual operation usually under a microscope. Now there is a new state-of-the-art metrology tool (KIS2010 Inspection System) for quantifying all parameters associated with the dicing process. The system provides computer controlled robotic inspection combined with onboard statistical data reduction software to display results. The goal of this paper is to provide other engineers working in defect and failure analysis an insight into the power of this metrology tool and how it can provide a firm basis for characterizing failures related to the dicing process.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 143-148, November 11–15, 2001,
... different from anything we have seen in past device technologies. The resolution of these new failure modes is not trivial to analyze. This case study will detail the diagnostic journey used to resolve one such new and unique failure, the “Star Crack”. electrical over stress electro static discharge...
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The fabrication of semiconductor devices is handling, processing and test verification intensive all of which present opportunities for electrical over stress (EOS) or electro static discharge (ESD) to occur. Well-documented models for ESD exist. These include Human Body Model (HBM), Machine Model (MM) and Charged Body Model (CBM), but such is not the case for EOS and its manifestations. In addition, as device technologies change and reduce in dimension these geometric reductions create increases in operating currents and magnetic fields located on the die surface. When there are occasions where devices are overstressed electrically in new device technologies, the manifestation or evidence of the EOS maintains the same appearance while physical dimensions have become much reduced. On occasions, the manifestation or evidence of EOS in some new device technologies tends to appear different from anything we have seen in past device technologies. The resolution of these new failure modes is not trivial to analyze. This case study will detail the diagnostic journey used to resolve one such new and unique failure, the “Star Crack”.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 491-495, November 1–5, 2015,
... Abstract Over the past several years there has been a large industry wide effort to change over from gold bonding wires to copper in order to minimize production costs. In certain cases this is not possible due to the relatively high hardness values of Cu [1], which leads to reliability issues...
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Over the past several years there has been a large industry wide effort to change over from gold bonding wires to copper in order to minimize production costs. In certain cases this is not possible due to the relatively high hardness values of Cu [1], which leads to reliability issues in the manufacturing process. Silver (Ag) wire has been proposed and successfully implemented in many instances where Cu wire was not practicable. Unfortunately, currently integrated decapsulation methods severely damaged or destroyed the silver wires and bonds, making it impossible to perform production controls and failure analysis. In this article we present a reliable and repeatable automated method to expose these die and wire bonds. By adding a dilute iodine solution to the nitric acid in an acid decapsulator, these packages can be fully opened without degrading the silver wires, allowing both mechanical and electrical testing on these devices.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 321-327, November 12–16, 2006,
... Abstract Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive...
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Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 128-132, November 2–6, 2008,
... have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged...
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Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 125-130, November 2–6, 2003,
... to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting...
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This paper correlates the reseat failure rates of a PCI option card to the use of thin gold plating across the contact fingers. This failure mechanism results in increased contact resistance and is often misdiagnosed due to its intermittent failure mode. As many new manufactures appear in Asia, the push for global competitiveness to achieve high volume and reduced costs can result in insufficient plating finishes being applied to the contact fingers. Compounding this problem is the fact the many companies use multiple raw board suppliers to meet these volume requirements. Many times the end user of the option card is unaware of the wide variation in contact plating thickness that may be present from one raw board source to another. Intermittent failures are one of the most common defects experienced in high volume assembly. Unless properly diagnosed, these failures can be attributed to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting approach is followed, isolating the true root cause of the actual failure can be missed. The difficulty in identifying the reseat problem is compounded by the fact that the failures are often intermittent in nature. While reseating may temporarily achieve sufficient mating between the board’s contact fingers and the connector contacts, it provides no long term fix. These unnecessary reseats also reduce the long-term durability of already thin plating affecting customer satisfaction and warranty costs. In the paper, we will expand on the theory behind the XRF plating thickness testing, including: • System theory • Test calibration • Part orientation • Test measurement criteria Additional analysis of metallurgical cross-sectioning was performed to correlate the XRF test readings to the actual plated layers. The measurements were completed by use of a SEM (Scanning Electron Microscopy).
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