This paper outlines a methodology which accurately identifies fault locations in Mixed Signal Integrated Circuits (ICs). The architecture of Mixed Signal ICs demands more attention during failure analysis because of the complexity of measuring both the analog and digital signals in a compact circuit. In this paper, the GHz range of data signal or radio frequency (RF) signal from an internal IC circuit will be extracted by a high-impedance active single probe in order to find the internal IC circuit failure locations. The advantages of using a single probe is that it can maneuver to extract data almost anywhere in the circuit, providing ranges of bandwidth in GHz with no loading effect on the circuits during measurement. The process of preparing a sample and extracting a signal will be described.

The failure localization on analog & mixed mode ICs in functional mode (AC signals) has become more and more challenging in the last few years. Due to an increasing integration and complexity of these devices, the number of defects, especially those named “soft”, raised considerably. The classical Dynamic Laser Stimulation (DLS) techniques showed some limitations when applied to analog & mixedmode ICs. The SDL (Soft Defect Localization) technique [1] based on binary output signal allows us to localize only the most sensitive areas. The defect in this type of circuits, which are very sensitive to the laser beam [2], is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in an analog way (the different sensitivity levels are visualized). To date, the T-LSIM technique [3], the Delay and the Phase Variation Mapping techniques were published [4, 5]. We have already had some interesting results by using these techniques [6] but not every “soft” defect case study could be resolved in that way. In this paper we propose to look at some different parameters which characterize an analog signal and can be used as an input for laser mapping. By applying a simple setup, without any additional sophisticated tool, we show on a “golden” commercial IC the added value of this analysis. We also deal with amplifying the weak signal variations induced by the laser beam scan which often are hidden by the high signal variations in analog or mixed-mode ICs.

This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

Due to the decreasing metal line size on complicated integrated circuit, non-destructive analysis strategy such as EMMI (Emission Microscope) is very significant to failure analysis, especially when special cold temperature failures are encountered. When combined with efficient schematic and layout analysis, the real defect can be localized without much microprobe work.

It is difficult to localize the soft defect on analog and mixed-signal ICs only by OBIRCH, because OBIRCH laser scanning module could not synchronize with the IC under functional test, and the failure modes on analog and mixed-signal ICs are complicated. In this paper, a dynamic synchronization method is proposed to localize the soft defect precisely only with an OBIRCH tool on analog and mixed-signal ICs. The methodology and system configuration are presented. A case is studied successfully on an analog and mixed-signal IC using this method.

Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.

First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.

In this paper, we discuss a set of techniques and analysis methodologies for the reverse engineering and functionality extraction of complex mixed-signal ICs with a special focus for security applications. Front and back side reflected light pattern images at different magnifications are used to identify circuit blocks. Time-integrated and time-resolved photon emission data is used to identify gate logic states, sequences of events, and specific functional activity. Backscattered electron and scanning transmission electron images mosaics are used to reverse engineer individual gates and observe local interconnects. Thermal imaging is used to aid in the functional block identification and analog gates analysis. Different advanced methodologies for tool automation, focusing, mapping, and image processing are also discussed in the context of our proposed electro-optical tester based technique.

In modern-day semiconductor failure analysis (FA), the need for computer-aided design (CAD) has extended beyond the sole physical layout to a much larger scope of integrated circuit (IC) design data, such as the source schematic and netlist. Due to the improved accuracy of predicted failures reported by test and diagnosis tools, it has become virtually mandatory to correlate the potential failing schematic features (e.g., nets and instances) to their corresponding location on the physical-CAD layout and actual device under test (DUT). This paper covers the latest advancements of utilizing IC design schematics for fast and accurate fault localization; along with some of the most-effective methodologies for efficient root-cause analysis.

Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

Possible reliability failure mechanisms on mixed-signal IC are reviewed and categorized. Based on the nature of reliability and low DPPM failures on mixed signal IC, an analysis flow is proposed including identification of individual failure mechanisms, extraction of the systematic problems, and implementation of corrective actions. Finally, a case of successful isolation of a specific defect without common electrical signature on mixed-signal devices is presented.

Soft defect localization techniques based on laser stimulation have become key techniques for a wide range of FA/debug issues. In this paper, we demonstrate the ability of these techniques to solve critical design issue in mixed-mode device for automotive application which includes analog, logic, RF and power. Utilizing a wide range of laser stimulation techniques, we have determined the most efficient approach for this device to achieve the shortest cycle time. We have established a clear link between fault isolation by laser stimulation techniques and the abnormal behavior of the device with relevant and complete simulation at transistor level.

The increasing electrical design and physical complexity of semiconductor devices, especially in the analog and mixed signal (AMS) applications, directly influences the development and evolution of fault isolation techniques. One of these techniques is Dynamic Laser Stimulation (DLS) which is widely used in the industry for effective identification of subtle failure mechanisms and soft defects especially for AC signal-related failures [1, 2]. However, for analysis of some complex AMS IC failure modes, the tool’s standard setup may not always be compatible with the biasing requirements of the device. For example, the setup would typically require expensive and intricate test systems (i.e. Automatic test equipment (ATE), SCAN tester, etc.) to be interfaced with the DLS tool for the analysis to be feasible and successful [3, 4]. This paper presents simple and practical techniques to implement DLS without the need for an expensive test support system. These techniques were applied in three different FA cases involving AMS ICs with complex and temperature-dependent failure modes. The results of subsequent analysis indicated success in isolating the exact defect sites.

This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

Soft Defect Localization (SDL) method has been a common failure analysis technique used in fault isolation of temperature dependent failures, however proper signal conditioning and conversion of the monitored signal into a pass/fail signal are critical in acquiring an accurate defect location. This paper presents case studies where LabVIEW software using NI-PXI test platform was successfully implemented to effectively convert the failure mode into a pass/fail signal which provided a reliable SDL result.

Internal IC probing has become an important tool for failure analysis and defect localization. Optical stimulation of logical transients enables the investigation of electrical pulse propagation through IC-regions which are not directly connected to an external input. The signal detection should be as directly as possible to avoid misinterpretation of experimental results, especially for time-resolved measurements. This paper describes the implementation of a capacitive coupling technique on a laser scanning microscope and on a needle prober. Results of static and time-resolved measurements are presented and compared to those obtained by OBIC measurements.

This paper presents a case study on reliability reject on a Freescale mixed-mode IC. It focuses on a novel use of one of most frequently used failure localization techniques: static emission microscopy (EMMI) to localize a failure due to an electrical transient behavior. This work helped Freescale to identify a wafer fab process limitation and contributed to test improvement.

This paper uses an interesting case study to highlight high-resolution pulsed thermal-induced voltage alteration (TIVA) with solid immersion lens (SIL) as a technique to isolate a temperature-sensitive failure in mixed-signal circuitry, followed by circuit analysis and nanoprobing to confirm a drive strength issue caused by a process change.

In this paper, we will present our solution to the problem of test based fault localization in the failure analysis laboratory environment. The test system described herein is currently used for a number of high power mixed signal application specific integrated circuits (ASICs) that incorporate functions including switching power supplies, charge pumps, high current drivers, precision references, ADCs/DACs, comparator circuits, and digital cores. The solution addresses the shortcomings of alternative options through modular construction, compact size, and use of a commercially available graphical software compiler to create the control code and graphical user interface (GUI).

Marginal internal leakage in mixed-signal devices at operating mode was isolated using a system evaluation board (SEB) and a highly sensitive infrared detector. Focused ion beam cross-section revealed a thin Ti/TiN metal residue (stringer) over two narrowly spaced metal lines. This is a quick and effective technique in isolating small leaky nets for integrated devices.