Customer-reported device failures that cannot be replicated during incoming retests present a significant challenge in semiconductor testing. These discrepancies often arise because customer applications subject devices to more extensive and prolonged stress conditions than standard final testing procedures allow. This paper presents a novel method for detecting subtle marginalities in main logic failures by modifying launch and capture pulses in transition delay patterns. Our approach enhances failure detection capabilities in failure analysis environments, particularly for marginal failures that initially pass automated test equipment (ATE) retesting despite customer-reported issues. We demonstrate the effectiveness of this technique through a case study where we successfully reproduced a customer-observed failure by adjusting the timing parameters. This method bridges the gap between standard test conditions and real-world application environments, enabling more accurate fault detection and validation.

During the last years, laser reflectance modulation measurements (i.e. LVI, CW-SIP etc.) have become indispensable tools for the analysis of logic circuits at frequencies in the megahertz range. In this paper we present a method to extend the usefulness of these methods to mixedsignal circuits driven at ultra-low frequencies in the kilohertz range. We show that by toggling the main power supply, information of the electric behavior can be easily obtained from analog structures, removing the need for tester-based stimulation. This method proved especially useful for the debugging of chip startup failures. We demonstrate this with two case studies. In a first case, a defect in the analog part shut down the digital part of the chip. This prevented the use of debugging methods such as the read-out of error registers or the use of scan chains. Conventional methods like photon emission microscopy and thermal laser stimulation were also not successful at finding the problem. However, laser-voltage imaging (LVI) of the analog circuit at key locations while toggling the chip power supply in the kilohertz range led us to the failing net. In a second case on a different product, we similarly identified a failing capacitor in the error logic by modulating the chip enable pin in the kilohertz range.

During yield ramp, quick turnaround times between production failures and the results of physical failure analysis are essential. In spite of the growing complexity of today's logic designs, a fast defect localization can be done by using diagnostic features implemented within standard test pattern generation tools. The diagnosis result can not only be used for fault localization but also for statistical analysis based on a large number of failing chips. This statistical approach enables the search for systematic yield detractors and leads to a faster product or technology ramp. This paper describes the necessary steps in order to set up statistical scan diagnosis, discusses the main failure analysis strategies and gives experimental results.

Digital fault localization for semiconductor devices failing Automatic Test Pattern Generation (ATPG) tests can be a very challenging task, particularly when the package of the device does not lend itself towards dynamic stimulation techniques. In the case of wire-bonded Ball-Grid-Array (BGA) devices, complete electrical functionality may only be preserved when access to the die is done from the frontside of the unit. This imposes significant limitations to the applicable optical fault isolation (OFI) techniques and their resolution in highlighting an anomaly, especially in advanced technology nodes that incorporate several metal layers. This paper explores the use of digital VDDLV supply domains as a means of activating defects inside specific logic areas, as an alternative to complex electrical setups, thus overcoming the package related limitations.

Soft Defect Localization (SDL) is a laser scanning methodology that is commonly used to isolate integrated circuits soft defects. The device is exercised by a functional vector set in a loop manner while localized laser heating stimulates a change in the pass/ fail (P/F) response at the location of the defect or critical path. Although SDL is effective for this purpose, long scan time arising from test overheads, can be a concern to turnaround time for root cause understanding. In this paper, an optimized scheme on synchronous SDL that has a potential to eliminate more than 90% of tester overheads and improve overall SDL test time by at least 17% is proposed. This is achieved by optimizing SDL test loop algorithm.

Infrared emission microscopy (IREM) is often the simplest and fastest fault isolation technique. In contrast to emission microscopy, laser-based techniques, such as thermally induced voltage alteration and light induced voltage alteration (LIVA), are not as dependent on leakage or the specific voltage of the defect to provide localization but are able to observe variations in the defective current drawn by the defect. This paper describes a method of applying LIVA to synthesized logic connected to large-scale power plane by controlling the amount of decoupling capacitance on the power supply. This has proven to provide very useful fault isolation beyond what is possible with emission microscopy. The logic LIVA result allowed the determination of locations of the two emissions seen in the IREM image as well as the word-line driver. This result provides a complete picture of the failure exact word-line driver-simplified physical failure analysis.

Laser voltage imaging techniques are widely used in failure analysis for detecting defects in digital circuitry. In case of scan chain failures that are substantially static, this is really the most suitable application. In this paper we explore and demonstrate the potential of this method for characterizing transition delay failures in combinatorial logic, through the real-time measurement of the behaviour of each transistor in the cell.

This paper presents the successful use of the novel inline product-like logic vehicle (PATO) during the last technology development phases of IBM's 22nm SOI technology node. It provides information on the sequential PATO inline test flow, commonality analysis procedure, and commonality signature trending. The paper presents examples of systematic defects uniquely captured by the product-like back end of the line layout. Moreover, this complex logic vehicle also uncovered a rich Pareto of more than 20 types of systematic and random defect mechanisms across the front end of the line, the middle end of the line, and the back end of the line. And more importantly, the non-defect found rate was kept below 20%. This achievement was possible by: leveraging high volume inline test ATPG scan fail data through the novel commonality analysis approach; and selecting the highest ATPG confidence defects representing a known commonality signature to physical failure analysis.

The Logic Mapper software created by Knights Technology bridges the gap between traditional yield enhancement techniques in the wafer fab and analytical failure techniques in the failure analysis (FA) laboratory. With Logic Mapper, fabs can test logic devices as easily as memory devices. Traditional logic chip yield enhancement techniques within product engineering and wafer fab yield enhancement organizations rely heavily on binsort functional test correlation to anticipate and correct semiconductor process issues. Some of the key shortcomings of these techniques are: · The inability to relate a particular bin’s fallout to a suspect process level. · The inability to distinguish a defect-driven yield issue from a device-integration issue. · The inability to establish a clear link between large populations of failed die. Logic Mapper resolves these key shortcomings by taking the output from functional testers and translating it from a list of failed scan chains into a list of suspected netlist nodes. Using Merlin’s FrameworkTM software, the netlist can be used to identify the X, Y coordinates of a suspected failing node; the failure analysis and yield enhancement engineers have created a starting point for investigating failures. These nodes can then be crossmapped from the circuit design onto the chip’s layout over multiple photomask layers within the design. The ability to translate a logic device’s binsort functional test fail data to defect traces is an advancement in the quality of test information provided for failure analysis and yield enhancement.

Logic mapping is the process of automatically correlating inline inspection defects with diagnosed faults from electrical testing. This paper presents a software based tool for this purpose and focuses on its specific use for impacting baseline yield enhancement. A detailed approach to utilizing logic mapping for this purpose is also presented. Results from a 10 wafer study using this tool are analyzed and show a defect correlation success rate of 31%. Additional work is presented for improving the logic mapping success rate and diagnosability of failures.

Logic diagnosis is the process of isolating the source of observed errors in a defective circuit, so that a physical failure analysis can be performed to determine the root cause of such errors. In this paper, we propose a new “Effect-Cause” based intra-cell diagnosis approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing (CPT) here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.

The root cause deconvolution (RCD) provides an easy-to-understand defect Pareto, together with targeted physical failure analysis candidates. Unfortunately, even the RCD analysis also has some assumptions and limitations, and its result cannot always be interpreted literally. This calls for a variety of conventional yield analysis techniques to be adopted in parallel to improve the confidence in the RCD results. This paper briefly introduces the RCD analysis and explains how it distinguishes itself from other conventional volume diagnosis analysis techniques. Its typical inputs and outputs are discussed as well. Next, the paper focuses on two case studies where the authors leverage RCD for logic yield improvement together with other conventional analysis techniques. It then proposes a comprehensive analysis system that is backed up by accumulating RCD results over time and across different design IPs.

Methodology remains an underdeveloped segment of the semiconductor Failure Analysis discipline. This paper describes a general formulation of scientific method for semiconductor Failure Analysis. The formulation creates a rigorous, customized analysis flow that flags both poorly-understood cause-effect relationships and missing techniques. It eases the application of basic inferential logic to the resulting analysis process, helping reduce errors in the analysis thought process. Finally, the methodology provides a uniform nomenclature and representation of the analysis process that lets the analyst describe complex flows in a simple and informative way. This general material has been presented by SDG Analytic, Inc. (now Metatech Corporation) in a public training course called “Precision Failure Analysis Logic.”

Failure analysis for Static Random Access Memory (SRAM) is the major activity in any microelectronic failure analysis lab. Originating from SRAM array structure, SRAM failure can be simple as single bit, paired bit or quad bit failures, whose defect is located at the failure location, or complicated as logic type failure involving WL or BL patterns or entire blocks, whose defect is often not at the failure location. For such SRAM logic type failures, failure analysis is more challenging and detailed fault isolation is necessary prior to physical failure analysis. This paper has demonstrated how to use SRAM decoder scheme knowledge, detailed layout tracing and Photon Emission Microscope (PEM) analysis to deal with the challenges and find the root causes for several cases of SRAM logic type failures.

With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.

Scanning Capacitance Microscopy (SCM) is an essential technique in semiconductor failure analysis. It is widely known in studies of dopant profiles and carrier concentration. Not only that, SCM can be utilized as an electrical fault isolation tool to localize a failing transistor. Compared to Conductive Atomic Force Microscopy CAFM, the main advantage of SCM is that it can be used on both Silicon on Insulator (SOI) and Bulk Silicon wafers. In addition, SCM can scan over a relatively large area in a shorter time than conventional nanoprobing methods. This paper presents case studies illustrating the effectiveness of SCM for die level top-down failure analysis on 45nm node SOI and 14nm FinFET bulk Si technologies.

For unique single failures, which tend to be the case in customer return and reliability failures, selecting another sample or performing root cause deconvolution is not an option, and if diagnostic tests are not conclusive, it becomes necessary to extend the effectiveness of automatic test pattern generator (ATPG) diagnosis in order to determine the failure mechanism. This paper proposes a way to improve resolution using single-shot logic and high-resolution targeted patterns. Two cases are presented to demonstrate the approach and show how it performed on actual failing units.

Due to the development of smaller and denser manufacturing processes most of the hardware localization techniques cannot keep up satisfactorily with the technology trend. There is an increased need in precise and accurate software based diagnosis tools to help identify the fault location. This paper describes the software based fault diagnosis method used within Philips, focusing on the features developed to increase its accuracy.

Before failure analysis (FA) can start, a product must get from the customer to the correct location, which is not always trivial, especially in larger companies with many FA labs. Automating and optimizing this routing, therefore reducing manual labor, misrouting, and turnaround time, requires the development of problem-solving methods utilizing both explicit and implicit knowledge. The first type refers to known routing rules, e.g., based on lab equipment or certifications, whereas the second type must be induced from available data, e.g., by analyzing customer descriptions using machine learning (ML) methods. Therefore, to solve the routing problem, we suggest a neurosymbolic integration of natural language processing methods into the symbolic context of a logic-based solver. The conducted evaluation shows that the suggested method can reduce the reships by appr. 33% while ensuring the fulfillment of all shipment constraints.

In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.