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logic processing

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Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 70-74, November 2–6, 2008,
...Abstract Abstract This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA ( E ffect, D efect, C ause, and A ction) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good...
Proceedings Papers

ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 479-485, November 12–16, 2000,
... on a number of CMOS microprocessors based on the 0.18 um logic process technology. The interferometric probing scheme will be described in detail and results will be presented. CMOS microprocessors failure analysis integrated circuits interferometer optical phase shift detection 479 Integrated...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 209-214, November 10–14, 2019,
... process development and ramp-up requires accurate methods for comparison of the desired layout with the manufactured result. Errors (or defects) can be manifested as logical (e.g. layout) as well as fabrication errors (e.g. dimensional deviations beyond specified tolerances). Application of 3D FIB-SEM...
Proceedings Papers

ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 319-322, November 15–19, 1998,
... as memory devices. Traditional logic chip yield enhancement techniques within product engineering and wafer fab yield enhancement organizations rely heavily on binsort functional test correlation to anticipate and correct semiconductor process issues. Some of the key shortcomings of these techniques...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 520-525, November 11–15, 2012,
...Abstract Abstract With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 295-299, October 28–November 1, 2018,
... pointed to the MIMCAP process integration. Product scan diagnostic was performed and several systematic failing logical nets were identified. Subsequent failure analysis showed open via contacts in the MIMCAP vicinity. A detailed layout analysis of the FA confirmed weak-points and repeating logic nets...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 389-396, November 14–18, 1999,
...Abstract Abstract Logic fault diagnosis or fault isolation is the process of analyzing failing random logic portions of a chip to isolate the cause of failure. Fault diagnosis or fault isolation (FI) plays an important role in multiple applications at different stages of design...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 184-190, November 2–6, 2003,
... is considered critical is done in the early stages of design, and circuit designer must implement this width limitation to the library cells of the new process. The implementation is especially costly for flip-flop (FF) design, these cells capture about 25-40% of the logic area. General limitation...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 341-347, November 3–7, 2002,
... poorly-understood cause-effect relationships and missing techniques. It eases the application of basic inferential logic to the resulting analysis process, helping reduce errors in the analysis thought process. Finally, the methodology provides a uniform nomenclature and representation of the analysis...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 458-462, November 6–10, 2016,
...Abstract Abstract The increase in complexity of process, structure, and design not only increases the amount of failure analysis (FA) work significantly, but also leads to more complicated failure modes. To meet the need of high success rate and fast throughput FA operation at the leading-edge...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 86-90, November 13–17, 2011,
...Abstract Abstract Logic diagnosis analyzes scan test failures and produces a list of potential defect locations and types. This information is often used as a starting point for a detailed physical failure analysis (PFA) process that locates the actual physical defect. One important criterion...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 539-542, November 3–7, 2002,
... an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 579-586, November 3–7, 2002,
...Abstract Abstract Logic mapping is the process of automatically correlating inline inspection defects with diagnosed faults from electrical testing. This paper presents a software based tool for this purpose and focuses on its specific use for impacting baseline yield enhancement. A detailed...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 322-326, November 5–9, 2017,
... an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure. ARM Cortex-A9 atomic force microscopy failure analysis fault isolation fault localization leakage current programmable logic devices scan chains system-on-chip devices...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 86-92, October 28–November 1, 2018,
...Abstract Abstract Combinational logic analysis (CLA) using laser voltage probing allows studying standard cells such as NOR or NAND gates as a whole, instead of individual transistors. The process involves building a reference library of laser probing (LP) waveforms and comparing them...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 65-72, November 9–13, 2014,
...Abstract Abstract Logic State Imaging (LSI) using Infra-Red Emission Microscopy (IREM) [1-4] has been an indispensable technology for silicon CMOS process development and product debug applications. Its main limitations are relatively poor spatial resolution due to the broadband near-infrared...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 128-132, November 2–6, 2008,
... of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 450-455, November 9–13, 2014,
... for a particular frequency band at cold temperatures only. This paper outlines the systematic isolation of a parasitic Schottky diode formed by a base contactcollector punch through process defect that pulled down the input of a NOR gate leading to the incorrect logic state. Note that this parasitic Schottky diode...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 204-208, November 10–14, 2019,
... is then repackaged and returned to the customer for validation of the circuit edit and the proposed logic or wiring design changes. A representative full FIB circuit editing process is shown in Figure 1 below. [1] Figure 1. Pictorial representation of the basic module FIB process for a single location wiring edit...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 122-128, November 15–19, 2020,
... tuned and placed ion beam in conjunction with process gases selectively uncovers internal circuitry, create functional changes in devices or the copper wiring pattern, and reseals the chip surface. When executed within reasonable limits, the revised circuit logic functions essentially the same...