Abstract Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful technical development, it is necessary to have a high speed interface that is complicated between the main processor and each IP block, but this can be problematic when the interface must support system level functions even though each IP alone does not have any problem. Most semiconductor companies and those doing Failure Analysis (FA) have adopted Automatic Test Equipment (ATE) because of its efficiency, but in cases where faulty products are detected at the customer site with their specific set of operating functions, the FA engineers have difficulties because of the challenge to convert customer’s functions to ATE test functions. To get through such a difficult situation, this paper presents a novel FA solution, utilizing Laser Voltage Probing (LVP) and set evaluation software and hardware, instead of ATE. This new FA technique can reduce the time to solve a system level application problem, improve FA quality with accurate timing analysis (detecting a 400ps signal glitch) and meet customer satisfaction by improving product quality. Fundamentally, the results of this paper compensated for the weakness in design procedures of IP blocks or products by adopting an additional simulation tool, which should prevent the recurrence of same-type errors.

Abstract A novel optical probing technique to measure voltage waveforms from flip-chip packaged complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) is described. This infrared (IR) laser based technique allows signal waveform acquisition and high frequency timing measurement directly from active PN junctions through the silicon backside substrate on IC’s mounted in flip-chip, stand-alone, or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug & failure analysis (FA) through-put time (TPT) as compared to backside electron-beam (E-beam) probing because of the elimination of backside trenching and probe hole generation operations.

Abstract Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.

Abstract We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].

Abstract Optical probing from the backside of an integrated circuit (IC) is a powerful failure analysis technique but raises serious security concerns when in the hands of attackers. For instance, attacks using laser voltage probing (LVP) allow direct reading of sensitive information being stored and/or processed in the IC. Although a few sensor-based countermeasures against backside optical probing attacks have been proposed, the overheads (fabrication cost and/or area) are considerable. In this paper, we introduce nanopyramid structures that mitigate optical probing attacks by scrambling the measurements reflected by a laser pulse. Nanopyramid structure is applied to selected areas inside an IC that requires protection against optical probing attacks. The fabrication of nanopyramids is CMOS compatible and well established for photovoltaic applications. We design the nanopyramid structure in ICs, develop the LVP attacking model, and perform optical simulations to analyze the impact of nanopyramids on LVP. According to the simulation results, the nanopyramid can disturb the optical measurements enough to make LVP attacks practically infeasible. In addition, our nanopyramid countermeasure has no area overheads and works in a passive mode without consuming any energy.

Abstract Laser-based dynamic analysis has become a very important tool for analyzing advanced process technology and complex circuit design. Thus, many good reference papers discuss high resolution, high sensitivity, and useful applications. However, proper interpretation of the measurement is important as well to understand the failure behavior and find the root cause. This paper demonstrates this importance by describing two insightful case studies with unique observations from laser voltage imaging/laser voltage probing (LVP), optical beam induced resistance change, and soft defect localization (SDL) analysis, which required an in-depth interpretation of the failure analysis (FA) results. The first case is a sawtooth LVP signal induced by a metal short. The second case, a mismatched result between an LVP and SDL analysis, is a good case of unusual LVP data induced by a very sensitive response to laser light. The two cases provide a good reference on how to properly explain FA results.

Abstract Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

Abstract Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes. Historically for signal probing, engineers analyzed signals from metal layers by using e-beam probing methods [1]. But due to the increased number of metal layers and the introduction of flip chip packages, new signal probing systems were developed which used time resolved photon emission (TRE) to measure signals through the backside. However, as the fabrication process technology continues to shrink, the operating voltage drops as well. When the operating voltage drops below 1.0V, signal probing systems using TRE find it harder to detect the signals [2]. Fortunately, Laser Voltage Probing (LVP) technology [3] is capable of probing beyond this limitation of TRE. In this paper, we used an LVP system to analyze and identify a functional shmoo hole failure. We also proposed the design change to prevent its reoccurrence.

Abstract In semiconductor industries, development of new technologies and new products generally follows a phase of yield improvement where Failure Analysis expertise is used to locate and fix killer defects and for design debug. When process and design reach a certain level of maturity, a second phase of optimization, qualification and reliability is executed in which Failure Analysis expertise is used for internal timing characterization of integrated circuit and results are compared with design/process simulations. In order to reduce the cost of testing during manufacturing, circuits embed Built in Self Timing Characterizer (BISC) for timing measurements inside critical functional blocks. Thanks to advanced integration, the last CMOS technologies allow high performance in terms of speed. Arithmetic and Logical Units (ALU) are able to work at frequencies greater than few GHz and some memories’ access time is lower than hundreds picoseconds. In the CMOS 40nm analysis case study presented in this paper, a BISC measurement of memories’ access times gives different results than what was expected from simulation. Internal probing becomes mandatory to understand this critical timing issue. A complete comparison is done between the 3 contactless probing techniques available in our laboratory which are the E-Beam Testing (EBT), Time Resolved Emission (TRE) and the recent Laser Voltage Probing (LVP) to highlight strength and weakness of each probing techniques in front of this timing related defect. We demonstrate that the LVP is an inevitable technique to address the nanometer-scale technologies in terms of spatial resolution, low voltage measurements and timing performance.

Abstract Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

Abstract Laser voltage imaging (LVI) and its derivatives are established techniques for isolating broken scan/JTAG chains which work on periodic signals, but are ineffective when debugging aperiodic signals. Laser voltage probing (LVP) works on one transistor at a time which makes it slow for certain debug. Laser voltage tracing (LVT), presented recently, has opportunity to perform an area investigation of aperiodic signals. This paper presents a few applications of this technique to fault isolation (FI).

Abstract In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the < 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the < 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.

Abstract Laser Voltage Probing (LVP) using continuous-wave near infra-red lasers are popular for failure analysis, design and test debug. LVP waveforms provide information on the logic state of the circuitry. This paper aims to explain the waveforms observed from combinational circuitries and use it to rebuild the truth table.

Abstract Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to <2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.

Abstract Visible light laser voltage probing (LVP) for improved backside optical spatial resolution is demonstrated on ultra-thinned samples. A prototype system for data acquisition, a method to produce ultrathinned SOI samples, and LVP signal, imaging, and waveform acquisition are described on early and advanced SOI technology nodes. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

Abstract Visible light laser voltage probing (LVP) for backside improved optical spatial resolution is demonstrated on ultrathinned bulk Si samples. A prototype system for data acquisition, a method to produce ultra-thinned bulk samples as well as LVP signal, imaging, and waveform acquisition are described on bulk Si devices. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

Abstract Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.

Abstract Results of experimental studies are presented which address a concern that gallium staining from FIB imaging during backside editing might degrade IR navigation as well as signal acquisition during probing of flip chips by such techniques as Picosecond Imaging Circuit Analysis (PICA) and Laser Voltage Probing (LVP). Although optical transparency does depend on gallium implantation dose, Ga staining is, however, not necessarily a limitation to the implementation of photon optical tools in the debug laboratory. Comparisons are made on the results from devices under the following conditions: with and without an anti-reflective (AR) coating, with and without XeF2 enhancement during FIB etching, and with confocal laser scanning microscope (CLSM) imaging and CCD-based IR microscope imaging.

Abstract Time-resolved photon emission (TRPE) results, obtained using a new superconducting, single-photon detector (SSPD) are reported. Detection efficiency (DE) for large area detectors has recently been improved by >100x without affecting SSPDs inherently low jitter (≈30 ps) and low dark-count rate (<30 s-1). TRPE measurements taken from a 0.13 μm geometry CMOS IC are presented. A single laser, time-differential probing scheme that is being investigated for next-generation laser voltage probing (LVP) is also discussed. This new scheme is designed to have shot-noise-limited performance, allowing signals as small as 100 parts-per-million (ppm) to be reliably measured.

Abstract Given the challenges FA Engineers have in fault localization, top-side analysis is facing a major challenge with today’s advanced packaging and shrinking of die sizes. At wafer and die level it is relatively easy to probe with little or no sample preparation. Greater challenges occur after the die is packaged. The difficulty further lies in non-destructively analyzing the die. Another issue with failure analysis is accurately deprocessing the device for probe pad deposition. Techniques like Electro Optical Probing (EOP) or Laser Voltage Probing (LVP) acquire electrical signals on transistors and create an activity map of the circuitry. In failure analysis, it is applied to localize defects. This paper discusses integrating EOP techniques in traditional FA to localize failure in mixed signal ICs. Three case studies were presented in this paper to establish the technique to be effective, quick and easy to probe non-invasively with minimal backside sample preparation.