Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful technical development, it is necessary to have a high speed interface that is complicated between the main processor and each IP block, but this can be problematic when the interface must support system level functions even though each IP alone does not have any problem. Most semiconductor companies and those doing Failure Analysis (FA) have adopted Automatic Test Equipment (ATE) because of its efficiency, but in cases where faulty products are detected at the customer site with their specific set of operating functions, the FA engineers have difficulties because of the challenge to convert customer’s functions to ATE test functions. To get through such a difficult situation, this paper presents a novel FA solution, utilizing Laser Voltage Probing (LVP) and set evaluation software and hardware, instead of ATE. This new FA technique can reduce the time to solve a system level application problem, improve FA quality with accurate timing analysis (detecting a 400ps signal glitch) and meet customer satisfaction by improving product quality. Fundamentally, the results of this paper compensated for the weakness in design procedures of IP blocks or products by adopting an additional simulation tool, which should prevent the recurrence of same-type errors.

A novel optical probing technique to measure voltage waveforms from flip-chip packaged complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) is described. This infrared (IR) laser based technique allows signal waveform acquisition and high frequency timing measurement directly from active PN junctions through the silicon backside substrate on IC’s mounted in flip-chip, stand-alone, or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug & failure analysis (FA) through-put time (TPT) as compared to backside electron-beam (E-beam) probing because of the elimination of backside trenching and probe hole generation operations.

Laser-voltage probing (LVP) and imaging (LVI) using a continuous-wave (CW) 1320-1340nm laser have become mainstream techniques for electrical fault isolation. A 1064nm laser with a 20% shorter wavelength offers immediate resolution advantages compared to 1320nm at a cost of increased intrusion. This paper explores the potential of CW 1064nm laser and identifies opportunities in fault isolation

Visible light laser voltage probing (LVP) for improved backside optical spatial resolution is demonstrated on ultra-thinned samples. A prototype system for data acquisition, a method to produce ultrathinned SOI samples, and LVP signal, imaging, and waveform acquisition are described on early and advanced SOI technology nodes. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

In semiconductor industries, development of new technologies and new products generally follows a phase of yield improvement where Failure Analysis expertise is used to locate and fix killer defects and for design debug. When process and design reach a certain level of maturity, a second phase of optimization, qualification and reliability is executed in which Failure Analysis expertise is used for internal timing characterization of integrated circuit and results are compared with design/process simulations. In order to reduce the cost of testing during manufacturing, circuits embed Built in Self Timing Characterizer (BISC) for timing measurements inside critical functional blocks. Thanks to advanced integration, the last CMOS technologies allow high performance in terms of speed. Arithmetic and Logical Units (ALU) are able to work at frequencies greater than few GHz and some memories’ access time is lower than hundreds picoseconds. In the CMOS 40nm analysis case study presented in this paper, a BISC measurement of memories’ access times gives different results than what was expected from simulation. Internal probing becomes mandatory to understand this critical timing issue. A complete comparison is done between the 3 contactless probing techniques available in our laboratory which are the E-Beam Testing (EBT), Time Resolved Emission (TRE) and the recent Laser Voltage Probing (LVP) to highlight strength and weakness of each probing techniques in front of this timing related defect. We demonstrate that the LVP is an inevitable technique to address the nanometer-scale technologies in terms of spatial resolution, low voltage measurements and timing performance.

Laser Voltage Probing (LVP) is an essential Failure Analysis (FA) technique that has been widely adopted by the industry. Waveforms that are collected allow for the analyst to understand various internal failure modes related to timing or abnormal circuit behavior. As technology nodes shrink to the point where multiple transistors reside within the diffraction-limited laser spot size, interpretation of the waveforms can become extremely difficult. In this paper we discuss some of the evolving challenges faced by LVP and propose a new technique known as Differential LVP (dLVP) that can be used to debug marginal failing devices that exhibit a pass/fail boundary in their shmoo plot. We demonstrate how separate pass and fail LVP waveforms can be collected simultaneously and compared to immediately identify whether logic is corrupted and when the corruption occurs. The benefits of this new technique are many. They include guarantees of equivalent pass vs. fail data independent of crosstalk, system noise, stage drift, probe placement, temperature effects, or the diffraction-limited resolution of the probe system. Implementing dLVP into existing tools could extend their effective lifetimes and improve their efficacy related to the demands posed by the debug of 5nm technologies and smaller geometries. We anticipate that fully integrated and evolved dLVP will complement workhorse FA applications such as Laser Assisted Device Alteration (LADA) and Soft Defect Localization (SDL) analysis. Wherein those techniques map timing marginalities propagating to, and observed by, a capture flop, dLVP can extend such capabilities by identifying the first instance of corrupted logic inside the flop and map the corruption all the way to the chip output pin.

Laser-based dynamic analysis has become a very important tool for analyzing advanced process technology and complex circuit design. Thus, many good reference papers discuss high resolution, high sensitivity, and useful applications. However, proper interpretation of the measurement is important as well to understand the failure behavior and find the root cause. This paper demonstrates this importance by describing two insightful case studies with unique observations from laser voltage imaging/laser voltage probing (LVP), optical beam induced resistance change, and soft defect localization (SDL) analysis, which required an in-depth interpretation of the failure analysis (FA) results. The first case is a sawtooth LVP signal induced by a metal short. The second case, a mismatched result between an LVP and SDL analysis, is a good case of unusual LVP data induced by a very sensitive response to laser light. The two cases provide a good reference on how to properly explain FA results.

Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.

We present an overview of Ruby, the latest generation of backside optical laser voltage probing (LVP) tools [1, 2]. Carrying over from the previous generation of IDS2700 systems, Ruby is capable of measuring waveforms up to 15GHz at low core voltages 0.500V and below. Several new optical capabilities are incorporated; these include a solid immersion lens (SIL) for improved imaging resolution [3] and a polarization difference probing (PDP) optical platform [4] for phase modulation detection. New developments involve Jitter Mitigation, a scheme that allows measurements of jittery signals from circuits that are internally driven by the IC’s onboard Phase Locked Loop (PLL). Additional timing features include a Hardware Phase-Locked Loop (HWPLL) scheme for improved locking of the LVP’s Mode-Locked Laser (MLL) to the tester clock as well as a clockless scheme to improve the LVP’s usefulness and user friendliness. This paper presents these new capabilities and compares these with those of the previous generation of LVP systems [5, 6].

Visible light laser voltage probing (LVP) for backside improved optical spatial resolution is demonstrated on ultrathinned bulk Si samples. A prototype system for data acquisition, a method to produce ultra-thinned bulk samples as well as LVP signal, imaging, and waveform acquisition are described on bulk Si devices. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

Laser Voltage Probing (LVP) using continuous-wave near infra-red lasers are popular for failure analysis, design and test debug. LVP waveforms provide information on the logic state of the circuitry. This paper aims to explain the waveforms observed from combinational circuitries and use it to rebuild the truth table.

Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.

Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes. Historically for signal probing, engineers analyzed signals from metal layers by using e-beam probing methods [1]. But due to the increased number of metal layers and the introduction of flip chip packages, new signal probing systems were developed which used time resolved photon emission (TRE) to measure signals through the backside. However, as the fabrication process technology continues to shrink, the operating voltage drops as well. When the operating voltage drops below 1.0V, signal probing systems using TRE find it harder to detect the signals [2]. Fortunately, Laser Voltage Probing (LVP) technology [3] is capable of probing beyond this limitation of TRE. In this paper, we used an LVP system to analyze and identify a functional shmoo hole failure. We also proposed the design change to prevent its reoccurrence.

Laser voltage imaging (LVI) and its derivatives are established techniques for isolating broken scan/JTAG chains which work on periodic signals, but are ineffective when debugging aperiodic signals. Laser voltage probing (LVP) works on one transistor at a time which makes it slow for certain debug. Laser voltage tracing (LVT), presented recently, has opportunity to perform an area investigation of aperiodic signals. This paper presents a few applications of this technique to fault isolation (FI).

Time-resolved photon emission (TRPE) results, obtained using a new superconducting, single-photon detector (SSPD) are reported. Detection efficiency (DE) for large area detectors has recently been improved by >100x without affecting SSPDs inherently low jitter (≈30 ps) and low dark-count rate (<30 s-1). TRPE measurements taken from a 0.13 μm geometry CMOS IC are presented. A single laser, time-differential probing scheme that is being investigated for next-generation laser voltage probing (LVP) is also discussed. This new scheme is designed to have shot-noise-limited performance, allowing signals as small as 100 parts-per-million (ppm) to be reliably measured.

Optical probing from the backside of an integrated circuit (IC) is a powerful failure analysis technique but raises serious security concerns when in the hands of attackers. For instance, attacks using laser voltage probing (LVP) allow direct reading of sensitive information being stored and/or processed in the IC. Although a few sensor-based countermeasures against backside optical probing attacks have been proposed, the overheads (fabrication cost and/or area) are considerable. In this paper, we introduce nanopyramid structures that mitigate optical probing attacks by scrambling the measurements reflected by a laser pulse. Nanopyramid structure is applied to selected areas inside an IC that requires protection against optical probing attacks. The fabrication of nanopyramids is CMOS compatible and well established for photovoltaic applications. We design the nanopyramid structure in ICs, develop the LVP attacking model, and perform optical simulations to analyze the impact of nanopyramids on LVP. According to the simulation results, the nanopyramid can disturb the optical measurements enough to make LVP attacks practically infeasible. In addition, our nanopyramid countermeasure has no area overheads and works in a passive mode without consuming any energy.

Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

Electrooptical investigations such as laser voltage probing (LVP) and dynamic laser stimulation (DLS) are very popular electrical fault isolation techniques (EFI) that use lasers on semiconductor circuits to study the functionality of transistors while the device is in operation. While many studies have been undertaken to understand interaction between laser and planar devices, three-dimensional devices such as FinFETs have interesting physiologies that have not been fully explored. In this work, we study the interaction of polarized light with the n-type metal oxide semiconductor (NMOS) FinFETs, experimentally and through Multiphysics simulations. We report highly directional electrooptical interactions in the FinFET. LVP signals are stronger when the laser used is polarized parallel to the fin and laser stimulation stronger when the laser used is polarized parallel to the gate. These findings affect future laser stimulation and probing investigations for EFI.

Hard functional and logic failures which are insensitive to temperature, voltage, or frequency have become increasingly difficult to debug in advanced technology nodes, especially when Photon Emission (PEM) analysis could not provide any leads and Dynamic Laser Stimulation (DLS) could not be used due to the nature of the failure (no pass/fail margin). Laser Voltage Imaging (LVI), which is an extension of the Laser Voltage Probing (LVP) technique, provides a visual map of active components that are toggling at a certain frequency. This technique is widely employed in scan chain debug due to its simplicity, efficiency, and accuracy. However, most of LVI applications in literature reviews only involve scan chain fault isolation. This paper will present alternative applications for LVI, apart from scan chain debug. One specific application is the debug of a broken signal path by sending a periodic signal as a stimulus to a GPIO pad and tracing the LVI signal through the path by frequency mapping. In this paper, the concept and methodology behind this fault isolation approach will be discussed in full detail. Furthermore, three case studies of different types of hard failures with different applications of LVI will also be presented: an IO functional failure, an ATPG (Automatic test pattern generation) SAF (Stuck At Fault) failure and a BSDL(Boundary scan description language) input interconnect failure, to illustrate how LVI could be deployed in fault isolation for those functional and logic hard failures.