Abstract Laser Assisted Device Alteration (LADA) or Soft Defect Localization (SDL) is commonly used to root cause device marginality due to functional or structural failures. At a high level, LADA involves setting the device under test (DUT) at its marginal state and using focused near infra-red laser beams to perturb sensitive circuitry [1]. Scanning the focused laser beam over the die can be a long and time-consuming process. In this paper, two LADA cases are presented, which involve a parametric measurement failure while running a dynamic ATE test. Using LADA technique, these two cases were root caused. These two cases also explain how a parametric measurement-based LADA can be setup on ATE, as well as a synchronization method independent of vectors in a pattern. Synchronization was necessitated in the 2nd case due to the asymmetric test program loop, as well as the long test program cycle time. There are many factors which impact LADA turnaround time and it can take anywhere between few seconds to one day. The two major factors are the size of the Area of Interest (AOI) and test program cycle time. Test program cycle time influences the laser “dwell time” for LADA. Dwell time, in simple terms, is the total time the laser is parked at each pixel. The laser can also be synchronized with the test program cycle, keeping the two always in phase. This is explained in Case 2, where LADA synchronization was implemented, and the analysis was successfully completed in time, even though the test cycle time was very long.

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuit. In this paper, the characterization of continuous wave 1340nm laser induced currents and the LADA failure rate show that a two photon absorption explanation for the LADA effect is not plausible. The following sections confirm the results of a 28nm-node nMOS transistor using a 2.45NA solid immersion lens. The effects of global heating to that of local laser heating are then compared. The paper shows that the LADA response time to approximately 1300nm irradiation is << 100ns. It explains LADA at approximately 1300nm, free carrier absorption in the silicon and in the local silicide layers, and presents selected 1320nm LADA images on 28nm-node devices. Finally, it shows 1064nm LADA images on the same structure that indicate that 1064nm interaction with transistors is related to free carrier absorption, rather than electron-hole pair creation.

Abstract In the case of conventional planar FET, Dynamic Laser Stimulation (DLS) is a very effective method to isolate marginal failure. Depending on laser sources, DLS is divided by Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). SDL uses 1320nm wavelength laser source in order to induce localized heat. On the other hand, LADA uses 1064nm wavelength laser source to generate photo carriers. But for the FinFET the effect of laser stimulation is not clear yet. This paper introduces the effect of laser stimulation on FinFET transistors based on wavelength, the so called LADA and two-photon LADA. The experimental data show changes in Vth and Idsat with different character for a single FinFET transistor. A case study further explains this laser stimulation effect via scan chain LVcc marginal failure analysis localized with 1320nm CW laser stimulation and nano-probing analysis.

Abstract In this paper, we report on the first observation and study of two-photon absorption (TPA) based laser assisted device alteration (LADA) using a continuous-wave (CW) 1340nm laser. The study was conducted using LADA systems equipped with high numerical aperture (NA) liquid and solid immersion lens objectives on Intel’s 45 nm and 32 nm multiprocessor units (MPU) and test chips. The power densities achievable using these lenses are similar to those reported in the literature for TPA in silicon of CW 1455nm light [1]. We show that the induced photocurrent has a quadratic dependence on the input laser power, a key indicator of two-photon phenomenon. Our results imply that even when using 1340nm wavelength CW lasers, there is a potential for laser invasiveness with the high power densities achievable using high NA objectives. Laser induced damage of the DUT is also a possibility at these high power densities, particularly with the solid immersion lens (SIL). However, we show that the DUT damage threshold can be increased by reducing the DUT’s temperature. Finally, we present results demonstrating a >40% improvement in localization of critical timing faults using TPA based LADA, when compared to traditional 1064nm wavelength (single-photon absorption) LADA.

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

Abstract A modulated laser beam in the form of a continuous pulse train is explored on Laser Assisted Device Alteration (LADA). We term this pulsed-LADA to differentiate from conventional continuous wave (cw)-LADA. It is found that a duty cycle of less than 0.9 at low frequency above 1 kHz is sufficient to experience significant enhancements in laser stimulation. Following this, a new derivative of LADA technique called Electrically-enhanced LADA (EeLADA) is developed. Experimental results to demonstrate its capability in improving diagnostic resolution and potential application to hard failure debug will be presented.

Abstract Pulsed-LADA is found to play an important role in the advancement of next-generation LADA and it is reported that tens of μs pulses with 10 kHz frequency is sufficient to observe enhancements in carrier injection. Electrically-enhanced LADA (EeLADA), based on pulsed-LADA, is introduced as a new fault localization method capable to overcome current limitation of Laser Assisted Device Alteration (LADA) application on soft failure and extends it to hard failure debug. We present the EeLADA methodology and experimental data to demonstrate its feasibility.

Abstract We describe a technique that is used to obtain timing information from laser assisted device alteration (LADA). The technique uses a non-pulsed laser scanning microscope to obtain timing information with a temporal resolution on the order of microseconds. Custom software is used to extract the timing information from the LADA images.

Abstract In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

Abstract Embedded cache size has dramatically increased with the advent of Intel Hyper-Threading and Multi-Core Technology, making many of the existing cache test validation method less and less practical, if not obsolete. As a result, the effort to sustain and improve array test quality, which is ever so critical to achieve DPM goals, is becoming a formidable challenge. In this paper, we present a test content validation procedure through novel application of Laser Assisted Device Alteration (LADA), i.e. soft fault injection in state elements, which had proven itself in Itanium® 2 array test quality improvement. While the procedure was originally targeting cache test content, the underlying concept has been successfully deployed to expedite scan test content and fault isolation tool validation.

Abstract Time-resolved laser assisted device alteration (TR-LADA) has interesting applications to reduce the spatial spread of LADA site, as well as benefit device design debug. This paper describes an implementation using a 1063nm wavelength nanosecond pulse-on-demand laser diode to obtain a timing resolution of 1-2 tester cycles and spatial resolution enhancements to LADA sites. We also present potential capabilities of TR-LADA in the debug of analog circuitry.

Abstract A system-on-chip processor (90 nm technology node) was experiencing a high basic function failure rate. Using a lab-based production tester, laser assisted device alteration, nanoprobing, and physical inspection; the cause of failure was traced to a single faulty P channel transistor. The transistor had been partially subjected to N doping due to poor photo-resist coverage caused by halation.

Abstract The work presented here is related to the utilization of computer aided design (CAD) Navigation tools in combination with images from Emission Microscope (EMMI) to improve the accuracy and efficiency of Failure Analysis. The paper presents the flow to quickly identify the failing device by taking the photon emission microscope image and CAD data as input. EMMI is used extensively for detecting leakage current resulting from device defects, e.g., gate oxide defects/ leakage, latch-up, electrostatic discharge (ESD) failure, junction leakage, etc. This emitted light is captured as hotspots on the image. A typical photon emission microscope image has a series of photon emission spots initiated by one physical defect. Not all emission spots may be defects; for example, emissions are shown during normal saturation or switching mode of the transistor. This results in multiple connectivity path between these spots which failure analysis (FA) engineer may want to analyze. The FA engineer wants to detect the one failed device which causes multiple other devices to show false hotspots. The work presented in this paper involves identifying all the devices beneath the hotspot areas, processing the connectivity of the found devices and extracting the schematic for all the devices beneath these hotspots. The connectivity between the devices could be direct connections through nets or indirect through “transmission gates”. The extracted schematic helps the FA engineer focus the FA work on critical devices such as a driver and enables faster and more accurate fault localization. The work in the paper shows the extraction of critical path of devices and their connectivity.

Abstract Presentation slides from the ISTFA 2021 tutorial, “[LADA and SDL: Powerful Techniques for Marginal Failures].”

Abstract We present an upgraded time-resolved LADA system, with a 25ps pulsed laser, integrated into a commercial laser scanning microscope used in failure analysis. We demonstrate the use of this system on 14nm/16nm finfet devices.

Abstract Circuit Edit and Optical Probe technologies must scale with Intel’s 2 year process cycle and the tick-tock design model. Geometry shrinking combined with revolutionary and evolutionary process changes such-as high-k and metal gate, lower-k interlayer dielectrics, and non-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide an overview of the Debug Block, we then provide an overview of the LADA, IREM, LVP, TRE, and FIB tools and their corresponding technical challenges for Intel’s next generation microprocessors. Finally we discuss the circuits, layout, and 32nm results.

Abstract We present a new method of imaging integrated circuits (ICs) using a dual-laser scanning confocal microscope. In this method we introduce physical and/or functional changes to the integrated circuit using the first ‘pump’ laser and then image the response of the circuit using the second ‘probe’ laser. We propose several novel applications of this imaging method. Specifically, we show how to image the flow of injected charge carriers and use the derived images to improve the resolution of material interfaces. We also show how to image changes to activity and laser voltage-probed waveforms and use the information to discover electrical connections between logic cells.

Abstract This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.

Abstract We present the first known images acquired using near-field scanning optical microscopy (NSOM) through backside silicon on functional integrated circuit samples with higher resolution than conventional fault isolation (FI) tools. NSOM offers the possibility of substantially-improved lateral resolution independent of excitation wavelength. Current FI techniques have challenged the resolution limits of conventional optics technology, even in the best solid immersion lens (SIL) to date. This poses a problem for future process technology nodes. This resolution barrier is a by-product of the diffraction limit. In Fourier terms, a conventional lens filters out highfrequency information and thus limits the resolution. In NSOM, by placing a tip with an aperture in extreme proximity to the surface it is possible to capture the near-field light that contains high-frequency information, thereby circumventing the diffraction limit. The tangible benefit is that the resolution is substantially improved. We show that NSOM can be used in backside subsurface imaging of silicon, mirroring the paradigm used in typical optical FI. We present optical reflectance data through ~100 nm of remaining backside Si on functional 22 nm CMOS IC parts with lateral resolution approaching 100 nm. We then discuss potential methods for using NSOM in practical backside fault isolation applications and for improving signal-to-noise ratio (SNR).

Abstract By inducing two-photon absorption within the device layer of a proprietary silicon test chip, the first nonlinear variant of X-variation mapping is reported by demonstrating frequency mapping of a ring oscillator circuit at 1.55µm.