This paper presents a large-volume workflow for fast failure analysis of microelectronic devices. The workflow incorporates a stand-alone ps-laser ablation tool and a FIB-SEM system. As implemented, the picosecond laser is used to quickly remove large volumes of bulk material while the Xe plasma FIB provides precise end-pointing to the feature of interest and fine surface polishing after laser ablation. The paper presents several application examples, including a full workflow to prepare artefact-free, delamination-free cross-sections in an AMOLED mobile display and the preparation of devices and packages (including flip chips) of varying size. It also covers related issues such as CAD navigation, data correlation, and the use of bitmap overlays for end-pointing.

Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

Ultra-short pulse laser ablation is applied to IC backside sample preparation. It is contact-less, non-thermal, precise and can ablate the various types of material present in IC packages. This study concerns the optimization of ultra-short pulse laser ablation for silicon thinning. Uncontrolled silicon roughness and poor uniformity of the laser thinned cavity needed to be tackled. Special care is taken to minimize the silicon RMS roughness to less than 1µm. Application to sample preparation of 256Mbit devices is presented.

A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, on a TSOP plastic package with an oversized silicon die, on a DIL ceramic package and on a CCD device. Feasibility of silicon thinning using laser ablation is also discussed.

As the semiconductor industry demands higher throughput for failure analysis, there is a constant need to rapidly speed up the sample preparation workflows. Here we present extended capabilities of the standard Xe plasma Focused Ion Beam failure analysis workflows by implementing a standalone laser ablation tool. Time-to-sample advantages of such workflow is shown on four distinct applications: cross-sectioning of a large solder ball, cross-sectioning of a deeply buried wire bond, cross-sectioning of the device layer of an OLED display, and removing the MEMS silicon cap to access underlying structures. In all of these workflows we have shown significant decrease in required process time while altogether avoiding the disadvantages of corresponding mechanical and chemical methods.

Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

By utilizing a NdYAG lamp pumped marking laser, along with unique mixes of specific acids, reproducible decapsulation of copper bonded devices without damage to the bond wires, packaging material, or to the silicon die circuitry itself can be achieved. With the copper bond wires, die, or substrate exposed, typical failure analysis methodology can then be applied to drive root cause failure analysis or device characterization.

In this paper different sample preparation strategies for fast and efficient failure analysis of 3D devices are reviewed and further explored. It will be shown that a combined workflow using laser ablation and plasma FIB milling provides best flexibility to cover most of the FA use cases. Laser ablation guarantees fast, coarse material removal and the subsequent plasma FIB milling provides fast removal of any damage or imperfections induced by the laser ablation, precise navigation to the region of interest, a high quality surface finish allowing direct SEM imaging and analytics such as EBSD and, if required the preparation of a thin lamella for TEM analysis.

We evaluated laser ablation and sandblasting as preparation methods for package related failures and for backside analysis of ICs. With laser ablation we uncovered gold wedges on an internal board of a PLFBGA package without damage of the gold wires and the board metallization. This was possible by optimization of the laser pulse energy and the pulse repetition rate and by limitation of the ablation area. Sandblasting showed to be a gentle way for backside thinning down to 60 μm silicon thickness. For a surface smoothness sufficient for IR imaging a subsequent planarization treatment is necessary.

This paper presents decapsulation solutions for devices bonded with Cu wire. By removing mold compound to a thin layer using a laser ablation tool, Cu wire bonded packages are decapsulated using wet chemical etching by controlling the etch time and temperature. Further, the paper investigates the possibilities of decapsulating Cu wire bonded devices using full wet chemical etches without the facilitation of laser ablation removing much of mold compound. Additional discussion on reliability concerns when evaluating Cu wirebond devices is addressed here. The lack of understanding of the reliability of Cu wire bonded packages creates a challenge to the FA engineer as they must develop techniques to help understanding the reliability issue associated with Cu wire bonding devices. More research and analysis are ongoing to develop appropriate analysis methods and techniques to support the Cu wire bonding device technology in the lab.

Decapsulation of plastic packaged components is frequently necessary for failure analysis or product development. Conventional techniques utilize an acid etch process, which is not compatible with copper and other acid-sensitive materials. There is limited ability to alter etch geometry or selectively decapsulate individual circuit elements. Laser ablation using a raster scanned Nd:YAG laser was used for selective decapsulation of temperature sensitive passive components in a PDIP packaged DC-DC converter. Copper welds, nylon insulated ferrite, and polyesterimide insulated magnet wire were decapsulated without damage, allowing failure analysis of a miniature transformer and its associated welded leads.

The trends towards 3D integration in microsystems technology and electronic packaging require that failure-analysis methods and target-preparation procedures are adapted to these emerging packaging technologies. The feasibility of laser-target preparation in microsystems is addressed in this paper, especially 3D integrated electronic devices. Various laser technologies were evaluated and the laser of choice was demonstrated to be appropriate for use with stacked packages. In addition, the laser preparation related Heat-Affected Zones (HAZs) were studied. The laser-energy absorption was determined by in situ heating-rate measurement, which enables precise prediction of HAZ extension by the use of Finite Element (FE) simulation. The advantage of this technique for removal rates compared to conventional techniques is discussed, as well as the combination of the excellent ablation rates of pulsed-laser ablation with the high accuracy of Focused Ion Beam (FIB) milling.

One method of reducing costs in the packaging sector is to switch from gold bond wires to copper. Thicker copper wires (over 2 mils) can be safely decapsulated using a ratio mixture of fuming acids. Some surface etching of the copper will occur, but the wire will remain electrically viable. Microwave Plasma can provide a safer alternative for decapsulating packages with copper bondwires and exposed copper metallization. In this paper, experimental deprocessing of copper bond wire and copper metallization using laser ablation and downstream microwave plasma has found that 1 mil stressed wires can be safely exposed and examined, showing slip plane fractures in the corner wires. Topside copper metallization remains intact, even the thin protective nickel plating. Sensitive copper metal structures on top of the passivation (such as antennas) will remain electrically viable following decapsulation with plasma, but are often lost and defective following acid decapsulation.

Over the past fifty year, lasers have found many, often groundbreaking applications in science and technology. The most important features of lasers are that photons are inherently free of contamination, extremely high energy densities can be focused in very small areas and the laser beam can be precisely positioned using deflection mirrors. By reducing pulse lengths from a few nanoseconds down to the picosecond or femtosecond range, material ablation is becoming increasingly “athermal”, i.e. structure damage by local heating is reduced to well below a few microns. In view of these outstanding characteristics of lasers, it is very surprising that sample preparation for microstructure diagnostics did not derive the advantages from laser micromachining. microPREPTM, is a new laser-micromachining tool developed by 3D-Micromac capable of making fast, clean, and efficient laser ablation available for the preparation of samples for transmission electron microscopy (TEM). The workflow follows a three-stage approach. First, a supporting basic structure is cut from the feedstock. Second, the supported structure is laser-thinned down to a few microns and third, the supported and laser-thinned structure is thinned using a focused ion beam or an ion broad beam. The examples presented in this paper support this approach and show it is ready to be applied in different areas of microstructure diagnostics and has very high potential for failure diagnostics.

This paper presents a new sample preparation process for front side access for die with organic dielectric layers that are encapsulated in plastic packages. The limitation of the standard failure analysis flow is firstly described, showing the damage caused by wet etching. Then, the decapsulation method combining laser ablation and plasma etching is presented. It is completed by the process optimization. The final process makes it possible to perform failure analysis on low-k/Cu technologies in plastic package either by the front side or by the backside of the die.

Integrated power devices (IPD, IC+MOSFETs) have gained popularity for their excellent power management performance and compact size. During the development, it was soon found that exposing the multi-die device for debug could be challenging. In the article, we will show how the traditional decapsulation method fails to expose the device properly for follow up analysis. We will then present a new technique using laser ablation + chemical/plasma etch that proves to work for IPD products. We will then present a complete FA example combining this decapsulation technique and many other advanced FA techniques to solve an elusive failure during the development phase of an IPD product.

Failure analysis laser inspection tool (FA/LIT) is a tool for the analysis of packaged devices. FA/LIT can routinely expose bond wires for inspection; however, concerns develop for the exposure of stitch bonds, the examination of small trace cracks, and any requirements to maintain electrical functionality of devices. Matching the FA/LIT settings based upon operation and sample material is critical in achieving good exposure of areas of interest with minimal damage. The use of practice samples, or areas away from the area of interest, to verify results before operations on actual FA parts is strongly recommended in this article. The installation of a grounded sample holder has been shown to greatly improve electrical integrity of samples during the laser ablation procedure. Use of the grounding sample holder improved electrical test results from 0% pass to 100% pass in advanced CMOS devices.

This paper presents a comparative study of backside sample preparation techniques with applicability to conventional as well as flip chip package types. We will cover mechanical (grinding and milling tools), chemical (wet and dry chemistries) and other approaches such as laser ablation. Backside sample preparation is very challenging. The preparation process flow starts with decapsulation of the ceramic or plastic package, continues with the die paddle removal, silicon thinning and finishes with silicon polishing. The techniques involved include mechanical, chemical and other novel approaches for ceramic and plastic package. Today, only CNC milling can cover the whole process for almost any kind of packages. Nevertheless, photo ablation is a rising technology for package decapsulation. In addition, chemical wet etch can be used to perform silicon thinning and polishing. We will illustrate the complexity of the process through examples. The first one is a ceramic package where the main issue is the hardness of ceramic. The second one is a TSOP package where the main challenge is the chip scaled package. Both will be observed through the IR emission microscope to demonstrate the efficiency of the preparation.

Driven by the cost reduction and miniaturization, Wafer Level Chip Scale Packaging (WLCSP) has experienced significant growth mainly driven by mobile consumer products. Depending on the customers or manufacturing needs, the bare silicon backside of the WLCSP may be covered with a backside laminate layer. In the failure analysis lab, in order to perform the die level backside fault isolation technique using Photon Emission Microscope (PEM) or Laser Signal Injection Microscope (LSIM), the backside laminate layer needs to be removed. Most of the time, this is done using the mechanical polishing method. This paper outlines the backside laminate removal method of WLCSP using a near infrared (NIR) laser that produces laser energy in the 1,064 nm range. This method significantly reduces the sample preparation time and also reduces the risk of mechanical damage as there is no application of mechanical force. This is an effective method for WLCSP mounted on a PCB board.

IC packages have been greatly improved over the past several years. With the adoption of Cu wires and new green EMC (Epoxy Molding Compound), the suppression of lead, the use of Cu pillars and the increased number of dies, the verification of the quality of the assembly and failure analysis becomes critical. Starting twelve years ago, LASER ablation was introduced as a means to facilitate the pre-decapsulation of packages aiming at a completion by wet chemistry (acids) or dry chemistry (plasma). The decapsulation process with acid at medium temperature (75°C) does not permit to keep the Cu wires intact. Our studies and work in the past several years has consisted in lowering the temperature of acid use in order to minimize the effect of acid attack on the Al pads and Cu wires. Currently the thinnest wires used are 0.6 mil in diameter (approximately 15 μm). In this article we will demonstrate that decapsulations at sub-ambient temperatures are now possible and give expected results. Moreover, openings at near ambient temperature reduce the component deformation and also the deformation of its constituents compared to decapsulations at medium or high temperature.