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For large area, high resolution SEM imaging applications, such as integrated circuit (IC) reverse engineering and connectomics [1-3], SEM instruments are limited by small, uncalibrated fields of view (FOVs) and imprecise sample positioning. These limitations affect image capture throughput, requiring more stage drive time and larger image overlaps. Furthermore, these instrument limitations introduce stitching errors in 4 dimensions of the image data, X, Y, Z and I (signal intensity). Throughput and stitching errors are cited challenges [2] and software alone cannot tenably correct stitching errors in large image datasets [3]. Furthermore, software corrections can introduce additional errors into the image data via the scaling, rotation, and twisting of the images. So software has proven insufficient for reverse engineering of modern integrated circuits. Our methodology addresses the challenges brought on by small, uncalibrated FOVs and imprecise sample positioning by combining the resolution and flexibility of the SEM instrument with the accuracy (of the order 10 nm), stability, and automation of the electron beam lithography (EBL) instrument. With its unique combination of high resolution SEM imaging (up to 50,000 pixels x 50,000 pixels for each image), laser interferometer stage positioning, and FOV mapping, the reverse engineering scanning electron microscope (RE-SEM) produces the most accurate large area, high resolution images directly acquired by an SEM instrument [4]. Since the absolute position of each pixel is known ultimately to the accuracy afforded by the laser interferometer stage, these images can be stacked (3D-stitched) with the highest possible accuracy. Thus, the RE-SEM has been used to successfully reconstruct a current PC-CPU at the 22 nm node.

The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

Photon Emission Microscopy (PEM) is one of the commonly used and powerful techniques for fault localization which uses a sensitive camera (like CCD or InGaAs) to detect a light (photon) emission from an electrically biased device. The fault localization of an open anomaly can be a challenge for the failure analysis. This paper discusses a novel technique for localization of an open fault on a thin-film resistor using induced photoemission method. In this proposed method, an emission site is induced at the open fault location on the thin-film resistor. This method was found to be effective and it increases the success rate for an open fault localization on a thin-film resistor.

The ability to expose a huge kerf/PCM (Process Control Monitor) test structure at the same level is limited from top down finger polishing. Also, in Scanning Electron Microscopy (SEM) the electron beam (e-beam) shift for electron beam absorbed current (EBAC) analysis is not able to cover the whole structure. The recently implemented technique described herein combines the focus ion beam (FIB) chemical enhanced milling method with EBAC analysis to stop the polishing at the upper layer and split the EBAC analysis into portions from the test structure. These help to improve the area of interest (AOI) evenness and enable the extension of the EBAC analysis.

Focused ion beam (FIB) techniques are often used when delayering semiconductor devices. However, using FIB technology for device delayering has limitations. One of these limitations prevents the exposure of a large slope area on the sample, which reveals all layers simultaneously. The delayering process is complex and requires prior process knowledge, such as cross-section architecture, composition, and layer uniformity. This paper discusses advances in semiconductor device deprocessing for product development, failure analysis, and quality control using low-energy, argon broad ion beam (BIB) milling. Ar BIB milling is a practical solution for accurate delayering of advanced microelectronic devices. Results of the spot milling of a whole 300 mm wafer experiment and top-down delayering of wafer pieces experiment show that successful device delayering can be achieved by either spot milling or layer-by-layer milling. These two strategies are easily achieved, for either small wafer pieces or full 300 mm wafer investigation.

As the semiconductor industry demands higher throughput for failure analysis, there is a constant need to rapidly speed up the sample preparation workflows. Here we present extended capabilities of the standard Xe plasma Focused Ion Beam failure analysis workflows by implementing a standalone laser ablation tool. Time-to-sample advantages of such workflow is shown on four distinct applications: cross-sectioning of a large solder ball, cross-sectioning of a deeply buried wire bond, cross-sectioning of the device layer of an OLED display, and removing the MEMS silicon cap to access underlying structures. In all of these workflows we have shown significant decrease in required process time while altogether avoiding the disadvantages of corresponding mechanical and chemical methods.

In the hardware assurance community, Reverse Engineering (RE) is considered a key tool and asset in ensuring the security and reliability of Integrated Circuits (IC). However, with the introduction of advanced node technologies, the application of RE to ICs is turning into a daunting task. This is amplified by the challenges introduced by the imaging modalities such as the Scanning Electron Microscope (SEM) used in acquiring images of ICs. One such challenge is the lack of understanding of the influence of noise in the imaging modality along with its detrimental effect on the quality of images and the overall time frame required for imaging the IC. In this paper, we characterize some aspects of the noise in the image along with its primary source. Furthermore, we use this understanding to propose a novel texture-based segmentation algorithm for SEM images called LASRE. The proposed approach is unsupervised, model-free, robust to the presence of noise and can be applied to all layers of the IC with consistent results. Finally, the results from a comparison study is reported, and the issues associated with the approach are discussed in detail. The approach consistently achieved over 86% accuracy in segmenting various layers in the IC.

To reconstruct discrete device threshold characteristics at tungsten contact level with atomic force probe (AFP), specific care in making drive current measurements is essential. Kelvin probing as well as the proper placement of the AFP probes themselves is an absolute requirement for insuring precise measurements. For this paper, NFET and PFET test structures employing 3 micrometer gate widths are used to simulate a sense-amp device. The results obtained using normal pad-level probing on a conventional probe station with results from an AFP nanoprober with and without Kelvin sensing are compared. These measurements are also compared with the nominal or expected design rule values. Experimental results comparing AFP Kelvin measurements at contact level on the same MOSFET test structure versus measurement obtained conventionally at pad level underscores the importance and value of AFP Kelvin measurements.

Bridging faults are a common failure mechanism in integrated circuits and scan-based diagnosis does a good job of isolating these defects. Diagnosis, however, can sometimes result in large search areas. Typically, these areas are caused by long repeater nets. When this happens, physical failure analysis will become difficult or impossible. This paper concerns itself with using a bridging fault analysis as a means of reducing these large search areas.

State-of-the-art semiconductor technologies use multiple copper metallization layers to route power and signals throughout the semiconductor device. These devices have four to six metal layers with the top layers predominately used to route the large power supply lines. To gain access to these lower signal lines, focused ion beam (FIB) must be used to cut large windows through the large power supply lines; this is very difficult. This paper demonstrates how EKC265 can be used as a copper metal etch to remove the copper of the power supply lines. This allows the FIB to cut large windows through the material layers to gain access to the lower metal layers for probing or FIB edits. Results are shown for FIB work using EKC265 and for FIB work without the using EKC265. EKC265 eliminates the need to use the FIB to remove copper giving a much more uniform milling result.

In this paper, we present a novel system and method for the automated mapping of pattern and spontaneous photon emission from very large areas of VLSI circuit using Solid Immersion Lens (SIL). To the best of our knowledge, this is the first time that such a technique has been developed and demonstrated on a real chip. The system being presented includes an automation software Application Programming Interface (API) to control the microscope used to acquire the images, an acquisition software that allows to automatically navigate the chip, move (hop) the SIL to the desired location, focus the image after the SIL landing, register the acquired images, and stitch them together to create a high resolution mosaic. In this paper, we will present, for the first time, a real life example involving thousands of images acquired from a 90 nm bulk technology test chip that were used to create a mosaic of more than 25 x 25 images covering a total area of approximately 400 x 400 μm2.

Scanning acoustic microscopy (SAM) has been in use for the analysis of small devices, mostly ICs, for quite some time. [1] This paper address the use of the technique on larger objects, such as solar panels, PCBs, and brazed cooling plates, the issues that arise, and solutions to mitigate those issues.

The standard Ga focused ion beam (FIB) technology is facing challenges because of a request for large volume removal. This is true in the field of failure analysis. This article presents the first combined tool which can fulfill this requirement. This tool offers the combination of a high resolution scanning electron microscope (SEM) and a high current FIB with Xe plasma ion source. The article focuses on failure analysis examples and discusses the different steps of extra large cross sections (deposition of protective layer, rough milling, and polishing). Several applications of the novel Xe plasma FIB/SEM instrument are shown with respect to the failure analysis. The performance of the instrument is tested and discussed in comparison to gallium liquid metal ion source FIB systems. Results show that the Xe plasma FIB offers much higher milling rate, greatly reducing the time necessary for many failure analysis tasks.

The proverbial needle in the haystack – locating a minute process defect or subtle ESD strike in a large sea of analog output power FETs can be just that. The premise of this paper is to discuss failure analysis techniques used to identify these elusive “needles”, specifically in large array power FET structures. Two case studies will be explored in detail – both of which are 250nm technology devices.

As semiconductor devices continue to decrease in size and pitch, demands for accurate microstructural analysis have increased to enable downward scaling. Critical dimension (CD) metrology is key to delivering process insights, but at such scales, rigorous metrology analysis providing high precision data may lack desired throughput. CD measurement using the scanning electron microscope (SEM) is a widely used technique, however, to acquire large area SEM images with high precision, multiple image stitching is currently required. In this paper, a new method for precise and efficient metrology analysis is introduced. This study demonstrates that large area imaging with ultra-high pixel resolution can deliver better throughput while maintaining the same level of precision that can be achieved by the traditional method.

In this paper, we discuss and showcase a 2-step defect isolation methodology by combining Focused Ion Beam “circuit editing” (FIB circuit edit) and Passive Voltage Contrast (PVC) imaging. The combo technique is an effective, robust, and time saving method for isolating defects in large area circuit structures for advanced nodes. The application of FIB circuit edits successfully enhanced the PVC efficiency in defect isolation. More importantly, the developed 2-step methodology improves failure analysis (FA) success rate and quality, and reduces FA turn-aroundtime (TAT).

As the new generation of microelectronics is pushed into smaller spaces and the yield production is pushing to lower the unoccupied spaces on chips, the local variation of stress has an influence on the component’s performance. This stress comes mainly from different thermal and mechanical properties of the materials used especially in 3D integrations like through silicon via (TSV) technology [1]. Through finite element simulation [2] the internal strain profile was modelled and based on these findings we devised a simulation model for a large area chunk lift out, to preserve the stress inside the material. Standard preparation method for strain measurement is to use a wafer dicing saw and subsequently focused ion beam (FIB) milling, to create lamellae with a defined geometry, close to the desired TSV. This method requires different equipment and knowledge base to achieve a lamella which is still contaminated by Gallium. Therefor we developed our own method based on an FE model of a large chunk lift out, where only a Xenon Plasma FIB is utilized until the local stress measurement using convergent beam electron diffraction (CBED) is measured in a transmission electron microscope (TEM).

Semiconductor devices are decreasing in dimensions and currently comprise stacks of ultrathin layers as in a spin-transfer torque magnetoresistive random-access memory (STTMRAM) device. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens for is desirable. In this work, we combine plan view Ga focused ion beam (FIB) and post-FIB Ar milling preparation to prepare TEM specimens from a STT-MRAM device. Post-FIB Ar milling technique as a final polishing step of plan view TEM specimens was shown to prevent exposure of the tunnel barrier layer that can be damaged by the Ga FIB beam. We discuss the plan view FIB preparation, post-FIB Ar milling step and image analysis of the TEM images.

Moore’s law has been a major driving force in the development of novel semiconductor devices and has continued to hold its relevance over the years. The resultant, smaller and more powerful, microprocessors not only cater to the ever-increasing demands of the existing needs but also are important enablers of novel applications and discoveries in different areas. Several critical features of these latest devices are in the atomic to nanometer scale, which has enhanced the necessity of a largescale transmission electron microscopy (TEM) imaging-based metrology and failure analysis for their process development. As a result, the automation of lamella preparation using focused ion beam (FIB) and TEM imaging has gathered an enormous momentum in last few years. A key aspect of automating a large-scale TEM sample preparation not only involves the calibration of a given FIB tool to achieve an acceptable and repeatable quality of TEM samples but also to ensure that sample quality is consistent across the entire fleet of toolsets. In this work, the performance of three ThermoFisher Exsolve toolsets using a common tool calibration method for both, lamella thickness and targeting, has been compared. It was found that in general, thickness of TEM lamella showed a larger variation as compared to targeting over the period of one month. Lamella thickness showed a decreasing trend, and it entailed a need of recalibrating the tools in an interval of two weeks so that the variation in both thickness and targeting for the fleet can be kept within the desired specifications of ±3 nm (2σ).

We describe a fully integrated solution for millimeter-scale delayering of both logic and memory semiconductor devices. The flatness of the delayered device is controlled by an artificial intelligence algorithm, which uses feedback from multiple analytical detectors to control milling parameter adjustments in real time. The result is the precise removal of device layers and a highly planar surface.