As silicon manufacturing processes move to smaller feature sizes, new silicon fault isolation and debug challenges arise. This paper presents a methodology for silicon fault isolation/debug that allows for simultaneous probing of multiple locations on the die using static infrared emission logic state imaging. Recent tool enhancements leading to more efficient fault isolation and debug are reviewed. Cases are presented from debug of 65nm products showing how this methodology was used to achieve very low throughput times on a variety of complex new failure mechanisms.

A technique is presented for mapping the logic states of CMOS integrated circuits by observing their static infrared emission. Application of the technique is shown in two case studies. The technique has the advantages of being non-invasive, having high observability and reduced complexity compared with dynamic probing techniques.

Logic State Imaging (LSI) using Infra-Red Emission Microscopy (IREM) [1-4] has been an indispensable technology for silicon CMOS process development and product debug applications. Its main limitations are relatively poor spatial resolution due to the broadband near-infrared photons emitted, and poor Signal to Noise Ratio (SNR) with low voltage and low leakage processes and products. Continuous-Wave Laser Scanning Microscope (CW-LSM) based Signal Imaging and Probing (CW-SIP) [5-9] technology is also widely used. It features inherently better spatial resolution than IREM, due to the use of monochromatic 1319nm or 1064nm laser light, and high SNR due to its weaker dependence on voltage and leakage, and, for signal imaging applications, the use of narrow band detection to reduce noise. However, CW-SIP can only detect modulating signals, so it couldn’t previously be applied to LSI. In this paper, we introduce an innovative approach that overcomes this limitation to enable Laser Logic State Imaging (LLSI). Actual fault isolation and design debug cases using this technology are presented to show its advantages in terms of resolution (>50% better), SNR (>2X better) and throughput time improvement, especially at low voltages (down to 500mV).

With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.

Infrared emission microscopy (IREM) is often the simplest and fastest fault isolation technique. In contrast to emission microscopy, laser-based techniques, such as thermally induced voltage alteration and light induced voltage alteration (LIVA), are not as dependent on leakage or the specific voltage of the defect to provide localization but are able to observe variations in the defective current drawn by the defect. This paper describes a method of applying LIVA to synthesized logic connected to large-scale power plane by controlling the amount of decoupling capacitance on the power supply. This has proven to provide very useful fault isolation beyond what is possible with emission microscopy. The logic LIVA result allowed the determination of locations of the two emissions seen in the IREM image as well as the word-line driver. This result provides a complete picture of the failure exact word-line driver-simplified physical failure analysis.

The need for failure analysis from the backside of the die has introduced new challenges in device analysis applications. Standard silicon based detectors are no longer as efficient due to the absorption of emission signals by the silicon substrate, which is now in the optical path between the device and the detector. The emergence of infrared detectors has offered a solution since emissions in this regime are not attenuated. This paper will describe a comparison made between a silicon detector and two of the most common IR detector materials.

A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.

Circuit Edit and Optical Probe technologies must scale with Intel’s 2 year process cycle and the tick-tock design model. Geometry shrinking combined with revolutionary and evolutionary process changes such-as high-k and metal gate, lower-k interlayer dielectrics, and non-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide an overview of the Debug Block, we then provide an overview of the LADA, IREM, LVP, TRE, and FIB tools and their corresponding technical challenges for Intel’s next generation microprocessors. Finally we discuss the circuits, layout, and 32nm results.

Resolution of optical fault isolation (FI) and nanoprobing tools needs to keep pace with the device downscaling to be effective for semiconductor process development. In this paper we present and discuss state-of-the-art FI and nanoprobing techniques evaluated on Intel test-chips fabricated on next generation process technology. Promising results were obtained but further improvements are necessary for the 7nm node and beyond.

Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

A laser based logic state imaging (LLSI) by activating transient voltage collapse (TVC) circuits of SRAM blocks is demonstrated. In order to induce a voltage modulation on a power rail, significant numbers of TVC units are activated. The image quality of LLSI strongly depends on a number of activated TVC circuits. From this experiment, it is concluded that an additional circuit or experimental setup is not necessary for LLSI.

Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

For more than 10 years, silicon thinning techniques have been relegated to an art form of mere necessity to enable complex optical probing and circuit edit analysis. Silicon thinning is a fundamental aspect of diagnostic analysis and while it is well-understood that limitations in the area of silicon thinning can severely limit high-quality diagnostic results, poor thinning results have generally been accepted as standard environmental operating conditions with which optical probe and circuit edit engineers must cope. Presented here is a scientific approach to thinning silicon to enable predictable high-precision, high-quality results. Remaining silicon thickness (RST) has been debated throughout the years because it was uncertain how much thinning was excessive. Primary perceived limitations included mechanical constraints (package / die warping) and post-thinning thermal control. Adding to the complexity of the discussion has been the fact that RST has been largely uncertain because analysis usually involved determining how much silicon was removed rather than how much silicon remains. All of these challenges have been overcome. A novel process has been developed to ultra-thin bulk Si to as low as 10um remaining Si thickness, eliminating the need for the Laser Chemical Etcher for circuit edit and improving optical emission probing considerably. This sample preparation process has been used on Intel Core2 Duo products with a success rate of 98%. Post FIB unit testing is a critical step in this debug process. A technique was developed to calibrate the change in thermal resistivity of the ultra-thin unit such that it will remain within 100ps of its original FMax performance in 90% of tests.

Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.

Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.

Post silicon validation techniques require backside sample preparation by silicon thinning techniques. The conventional fixture to this preparation on large die packages causes silicon to crack. A new “4-point bending” fixture was developed to reduce silicon bending strain during thinning to eliminate silicon cracking. This new fixture and technique improved remaining silicon thickness uniformity as well as process time.

The aim of this paper is to present a typical bridge defect case inside digital circuitry, from diagnosis to emission point of view. Specific considerations have allowed to establish the exact point of failure. Keywords— bridge defect, aggressor and victim, region of intersection

Photon Emission Microscopy (PEM) analysis is one of the most common used FA techniques to identify the root cause of failures within ATPG scan logic due to its ease of setup and less invasive nature. While conducting photon emissions, the device is made to operate in the fail mode by running a production test vector to look for anomalous emissions or hot spots that could narrow down the area of interest (AOI) for subsequent Physical Failure Analysis (PFA). However, if there is no clue from emission analysis in the case of a hard failure with no sensitivity to voltage, frequency, or temperature, FA debug will be challenging. This paper shows how PEM analysis success may be further improved through logic state circuit study using a DFT ATPG diagnostic platform. Logic state truth table and its relative test pattern will be built based on the diagnostic data using in-house scripts, and the test program can then be changed to the required condition of the circuitry. With the altered logic state, new emission data can be collected, which could potentially reveal new clues to the investigation.

A breakthrough approach was developed in which failure analysis (FA) of advanced microprocessor was carried out without the use of defect localization equipment. This technique enables the reading of internal signal value without the use of any physical probing method. This method demonstrates the same FA capability with higher success rate and shorter analysis time.

We present the first known images acquired using near-field scanning optical microscopy (NSOM) through backside silicon on functional integrated circuit samples with higher resolution than conventional fault isolation (FI) tools. NSOM offers the possibility of substantially-improved lateral resolution independent of excitation wavelength. Current FI techniques have challenged the resolution limits of conventional optics technology, even in the best solid immersion lens (SIL) to date. This poses a problem for future process technology nodes. This resolution barrier is a by-product of the diffraction limit. In Fourier terms, a conventional lens filters out highfrequency information and thus limits the resolution. In NSOM, by placing a tip with an aperture in extreme proximity to the surface it is possible to capture the near-field light that contains high-frequency information, thereby circumventing the diffraction limit. The tangible benefit is that the resolution is substantially improved. We show that NSOM can be used in backside subsurface imaging of silicon, mirroring the paradigm used in typical optical FI. We present optical reflectance data through ~100 nm of remaining backside Si on functional 22 nm CMOS IC parts with lateral resolution approaching 100 nm. We then discuss potential methods for using NSOM in practical backside fault isolation applications and for improving signal-to-noise ratio (SNR).