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Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 204-208, November 10–14, 2019,
.... GLOBALFOUNDRIES began a project to create a more robust repeatable resistive structure by removing several variables. Rather than direct writing lines onto a top surface layer, a confined deposition based on the concepts of dual damascene processing used with copper layers in modern semiconductor fabrication...
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Focused Ion Beam (FIB) circuit edit allows for rapid prototyping of potential semiconductor design changes without the need to run a full manufacturing cycle in a semiconductor Fab. By FIB editing a completed module, thorough testing on the bench or in a full system can be achieved. Logic can be toggled, validation of speed enhancements performed, and constructive and destructive failure analysis can be enabled. In order to fulfill all the needs of clients in a rapidly evolving SOC driven market, simply modifying existing devices by “rewiring” circuits is becoming insufficient. Often the team is tasked with making very repeatable structures to aid the circuit analysis group. These include relatively precise resistors for tuning RF circuits (part of an RC network), adding known loads or delays, et cetera. Naturally resistive FIB deposited metal lines connected to the existing circuitry can be used in this capacity. FIB chip edit is considered to be a “Direct Write” process. The beam pattern in conjunction with process gases defines the regions of milling and deposition. Unfortunately, FIB edit is rarely an exact science. In many cases, a number of characteristics seem to be outside the realm of precise repeatable control. This is evident not only in individual tool operational logs but also in FIB tool matching, where maintaining identical system performance within the lab is difficult or nearly impossible. These characteristics are highly dependent on precursor reservoir composition and flow, surface adsorption conditions, beam patterning integrity, and the total interaction space of competing back sputtering during the new material structure formation. Due to these factors, the shape, composition and electrical performance of metal and insulator depositions vary over an often unacceptable range. As a result, we were not meeting the needs of some critical customer applications. Direct written precision resistive structures displayed several issues for which iterative edits were required to compensate for variability. When attempting to create an exact resistance, this process was not reliable, nor was it repeatable enough for accurate circuit performance trimming. Space-constrained serpentine resistors or multiple discrete resistors side-by-side showed the greatest process variability. Metal deposition processes tend to be somewhat self-limiting, so thick boxprofile lines are difficult to form. Conductive material deposited outside of the pattern definition (overspray) results in line-to-line leakages. Attempts to remove the overspray thru ion beam assisted etch-back tends to damage the deposited conductors and underlying insulators. The low-k region between lines can become cross-linked, experience gallium doping, and become tungsten impregnated. This lowered the resistivity of the insulator, increased the resistivity of the conductor, and produced variability in the device which was especially an issue when dealing with varying initial substrates. GLOBALFOUNDRIES began a project to create a more robust repeatable resistive structure by removing several variables. Rather than direct writing lines onto a top surface layer, a confined deposition based on the concepts of dual damascene processing used with copper layers in modern semiconductor fabrication will be employed. The damascene process begins with the definition of a box to be filled with a conductive material. The process of ion beam gas assisted anisotropic etching/milling has a far more predictable outcome than ion beam induced deposition. It is possible to create a surface box mill or even a deep drilled via of desired dimensions with a more consistent repeatability. Deposition of tungsten into a confined region using, for example, a W(CO)6 precursor and a Ga+ ion beam results in an excellent via fill. Using this behavior, precision resistors can be created with metal deposition within the trenches which are created by the gas assisted mill. An enclosed space can be filled nearly void-free, and has repeatable electrical parameters. The self-limiting factors with tungsten deposition go away as sputtered material becomes trapped within the well resulting in a near limitless Zheight potential. The constant dielectric with a uniform and contained tungsten fill can allow for a well-defined resistivity for the FIB deposited tungsten material. Having a known resistivity, calculation of dimensions for resistive and inductive structures during the design process becomes feasible. With process variability under control, structures can be formed reliably enough to offer this as a service to customers.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 295-299, October 28–November 1, 2018,
... Abstract A BEOL compatible Metal-Insulator-Metal capacitor (MIMCAP) was successfully developed for GlobalFoundries 14nm technology node, and subsequently introduced on customer designs as decoupling capacitors. The lead production silicon wafers with MIMCAP showed good functionality at wafer...
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A BEOL compatible Metal-Insulator-Metal capacitor (MIMCAP) was successfully developed for GlobalFoundries 14nm technology node, and subsequently introduced on customer designs as decoupling capacitors. The lead production silicon wafers with MIMCAP showed good functionality at wafer SORT functional test. However, upon testing more wafers, it became evident that the wafer center was impacted by abnormal scan logic fallout. The observed yield loss did not correlate with the MIMCAP scribe line Health Of Line (HOL) structures and the failure root cause could not be directly pin pointed to the MIMCAP process integration. Product scan diagnostic was performed and several systematic failing logical nets were identified. Subsequent failure analysis showed open via contacts in the MIMCAP vicinity. A detailed layout analysis of the FA confirmed weak-points and repeating logic nets allowed identifying a chip design topography issue resulting in a narrower process window compared to the scribe line MIMCAP HOL structure. Thanks to this knowledge the MIMCAP process was further optimized and the wafer center fallout was fully recovered in volume production.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, i-iii, November 10–14, 2019,
... Dr. Felix Beaudoin Member at Large GLOBALFOUNDRIES Ms. Rebecca L. Holdford Member at Large Texas Instruments Mr. Ted Lundquist Member at Large Zeiss Smt Pcs Ms. Renee Parente Member at Large Advanced Micro Devices (amd) Dr. Tom Schamp Member at Large MAS Ms. Mary Anne Jerson Administrator, Affiliate...
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Listings of the EDFAS 2019-2020 Board of Directors and ISTFA 2019 Organizing Committee, Activities Chairs, and Technical Program Committee.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, iv-vi, November 5–9, 2017,
... at Large Consultant Mr. Ryan Ross Member at Large NASA Jet Propulsion Laboratory Dr. Sam Subramanian Member at Large NXP Semiconductors Board Committees Position Affiliation Dr. Felix Beaudoin EDFA Chair GlobalFoundries Dr. Mayue Xie Education Chair Intel Corp. Dr. Thomas Moore Membership Chair Waviks, Inc...
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Listings of the EDFAS 2017-2018 Board of Directors, the ISTFA 2017 Organizing Committee and Activities Chairs, and other contributors and committee members.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, iii-v, November 6–10, 2016,
... Member at Large Consultant Mr. Ryan Ross Member at Large NASA Jet Propulsion Laboratory Dr. Sam Subramanian Member at Large NXP Semiconductors Board Committees Position Affiliation Dr. Felix Beaudoin EDFA Chair GlobalFoundries Dr. Mayue Xie Education Chair Intel Corp. Dr. Thomas Moore Membership Chair...
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Listings of the EDFAS 2016-2017 Board of Directors, the ISTFA 2016 Organizing Committee and Activities Chairs, and other contributors and committee members.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, iii-v, November 1–5, 2015,
... Corporation Case Studies and the FA Process Zhigang Song, GlobalFoundries Rose Ring, GlobalFoundries Malta Detecting Counterfeit Microelectronics Robert Champaign, Raytheon Network Centric Systems Joe Colangelo, Raytheon Network Centric Systems Device Failure Analysis Victoria Bruce, Qualcomm Incorporated Ted...
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Listings of the EDFAS 2015-2016 Board of Directors, the ISTFA 2015 Organizing Committee and Activities Chairs, and other contributors and committee members.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, iv-v, October 28–November 1, 2018,
... 1, 2018, Phoenix, Arizona, USA DOI: 10.31399/asm.cp.istfa2018fm01 Copyright © 2018 ASM International® All rights reserved www.asminternational.org 2018 ORGANIZING COMMITTEE Ms. Efrat Moyal General Chair LatticeGear Dr. Felix Beaudoin Vice General Chair GLOBALFOUNDRIES Dr. David Grosjean Technical...
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Listings of the EDFAS 2017-2018 Board of Directors, the ISTFA 2017 Organizing Committee and Activities Chairs, and other contributors and committee members.
Proceedings Papers
ISTFA2022, ISTFA 2022: Tutorial Presentations from the 48th International Symposium for Testing and Failure Analysis, iii-vi, October 30–November 3, 2022,
... GLOBALFOUNDRIES EDFAS Board Members Dr. James J. Demarest Dr. Felix Beaudoin Ms. Renee Parente Dr. Lee Knauss, FASM Position President Vice President/Finance Officer Secretary Immediate Past President Affiliation International Business Machine GLOBALFOUNDRIES Advanced Micro Devices (AMD) Booz Allen Hamilton Mr...
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Listings of the EDFAS 2022 Board of Directors and the ISTFA 2022 Organizing Committee and Session Chairs.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, iii-vi, October 30–November 3, 2022,
... GLOBALFOUNDRIES EDFAS Board Members Dr. James J. Demarest Dr. Felix Beaudoin Ms. Renee Parente Dr. Lee Knauss, FASM Position President Vice President/Finance Officer Secretary Immediate Past President Affiliation International Business Machine GLOBALFOUNDRIES Advanced Micro Devices (AMD) Booz Allen Hamilton Mr...
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Listings of the EDFAS 2022 Board of Directors and the ISTFA 2022 Organizing Committee and Session Chairs.
Proceedings Papers
ISTFA2021, ISTFA 2021: Tutorial Presentations from the 47th International Symposium for Testing and Failure Analysis, iii-v, October 31–November 4, 2021,
... Beaudoin GLOBALFOUNDRIES EDFAS Board Members Dr. James J. Demarest Dr. Felix Beaudoin Ms. Renee Parente Dr. Lee Knauss, FASM Position President Vice President/Finance Officer Secretary Immediate Past President Affiliation International Business Machine GLOBALFOUNDRIES Advanced Micro Devices (amd) Booz...
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Listings of the EDFAS 2021-2022 Board of Directors and ISTFA 2021 Organizing Committee and Session Chairs.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, iii-v, October 31–November 4, 2021,
..., Arizona, USA DOI: 10.31399/asm.cp.istfa2021fm01 Copyright © 2021 ASM International® All rights reserved. www.asminternational.org EDFAS 2021-2022 BOARD OF DIRECTORS EDFAS President Dr. James J. Demarest International Business Machine EDFAS Vice President Dr. Felix Beaudoin GLOBALFOUNDRIES EDFAS Board...
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Listings of the EDFAS 2021-2022 Board of Directors and ISTFA 2021 Organizing Committee and Session Chairs.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, i-ii, November 15–19, 2020,
... GLOBALFOUNDRIES EDFAS Board Members Position Affiliation Dr. James J. Demarest President International Business Machine Dr. Felix Beaudoin Vice President/Finance Officer GLOBALFOUNDRIES Ms. Renee Parente Secretary Advanced Micro Devices (amd) Dr. Lee Knauss, FASM Immediate Past President Booz Allen Hamilton Mr...
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Listings of the EDFAS 2020-2021 Board of Directors and EDFAS 2020 Virtual Workshop Organizing Committee and Activities Chairs.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 153-155, October 28–November 1, 2018,
..., Kok Hin (Rick) Teo, Wayne Zhao, Joshua Moore, Laurent Dumas GLOBALFOUNDRIES, Malta, NY, USA Abstract Through inline processing of a prospective Spin on Hardmask (SOH) material, bubble defects were observed randomly across a wafer. Several complementary FA techniques were utilized to characterize...
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Through inline processing of a prospective Spin on Hardmask (SOH) material, bubble defects were observed randomly across a wafer. Several complementary FA techniques were utilized to characterize the bubble defects including SEM, TEM, and chemical analysis techniques. The root cause of defect formation was identified as a raw material imperfection in SOH, which led to excessive outgassing. Imperfections within the substrate formed nucleation sites for outgassing of SOH material forming bubbles, which allowed voids to propagate. These findings led to implementation of greater quality control methods by the raw material manufacturer.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 203-207, November 3–7, 2013,
... fault isolation IC devices semiconductor manufacturing Advantage of AFP nanoprobing on the 28nm technology failure analysis C.Q. Chen, G.B. Ang, S.P. Zhao, Q. Alfred. N. Dayanand, K. Dnyan, B.H. Liu Failure Analysis group, Quality and Customer Enablement (QCE) department, GLOBALFOUNDRIES Singapore...
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As the rapid developments of semiconductor manufacturing technologies, the CD of the device keep shrinking. The IC devices have a smaller feature sizes and higher densities, and thus there are many challenges come up in terms of the failure analysis and localized device characterization. Besides the challenge of smaller feature size, there is another challenge as well. Some of the traditional FA method can no longer be employed on advanced technologies, such as 28nm and beyond. Quickly and successfully isolating the failed location and obtaining electrical signature of the defect has become more of a challenge, especially for the device level analysis and characterization. AFP nanoprobing system provides some solutions to advanced nodes fault isolation through its AFM imaging mode of CAFM.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 564-567, November 6–10, 2016,
... imaging laser voltage probing SRAM Fault Isolation of DQ Failures in 14nm SRAM using Laser Voltage Imaging and Probing K. A. Serrels, A. Kalarikkal, A. M. Jakati, and G. Dabney GLOBALFOUNDRIES, FAB8 Center for Complex Analysis, Electrical Fault Isolation Group, Characterization Division, 400 Stone...
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Through custom test pattern generation and SRAM design analysis, we present the first demonstration of Laser Voltage Imaging (LVI) and Probing (LVP) for the successful fault isolation and physical analysis of DQ failures within a 14nm SRAM macro. These findings revealed the fail site to reside within the I/O circuitry of the associated failing pin, a previously overlooked location as common block failures are typically associated with physical anomalies within the SRAM periphery.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 568-570, November 6–10, 2016,
... for pursuing precise analysis of process evaluation and development in a 300mm fab at the East Fishkill (EFK) site of GLOBALFOUNDRIES. Full wafer usage for CLM process maintains integrity of wafers, since the CLM tool is a 300mm dual beam (FIB and SEM) suitable for a manufacturing environment. Therefore...
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This work presents a novel method of continuous improvement for faster, better and cheaper TEM sample preparation using Cut Look and Measure (CLM). The improvement of the process is executed by operational monitoring of daily beam conditions, end products, bulk thickness control, recipe usage and tool running time. This process produces a consequent decrease in rework rate and process time. In addition, it also increases throughput with better quality TEM samples.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 574-577, November 11–15, 2012,
..., Zhao Si Ping QRA Department, GLOBALFOUNDRIES Singapore, 60 Woodlands Industrial Park D, Street 2, Singapore 738406 Yao Yuan, Fab 7, Process Integration, GLOBALFOUNDRIES Singapore, 60 Woodlands Industrial Park D, Street 2, Singapore 738406 Teo Kim Hong, Chen Ye, Tee Irene, Lee Gek Li, Chen Changqing...
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Abnormal inline defects were caught after nitride spacer etching processes. Detailed MEBES layout checking and inline SEM inspection revealed that such defects always appeared at the boundaries in between PFETs and NFETs regions. The microstructure and chemical composition of the defects were analyzed in detail by various TEM imaging and microanalysis techniques. The results indicated that the defect possessed core-shell structure, with oxide core and nitride shell. Based on the TEM failure analysis results and manufacturing processes, we conclude that the defects originated from PR fencing due to the PR hardening during PFET and NFET LDD/Halo implantation. The oxide core was generated during oxide spacer formation using an ozone-TEOS process, which was responsible for the nitride spacer under-etch issue.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 38-41, November 15–19, 2020,
..., Thirukumaran Mahalingam1, Nuh Yuksek1, Lu Yuan1, Wang Tao1, Lillian Li1, Sushruth Goud Perumalla1, Shweta Arora2, Trejo Rust1 GLOBALFOUNDRIES, Malta, New York, USA GLOBALFOUNDRIES, Bengaluru, India Introduction A new low level systematic voltage sensitive scan chain fail pattern in the wafer donut region...
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Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 347-355, November 11–15, 2012,
... microscopy A Proof for the Possibility of Ce-oxide from CMP Residuals In Si-wafers by Analytical TEM Wayne Zhao* and Liem Do Thanh GLOBALFOUNDRIES Inc., Hopewell Junction, NY 12533 2070 Route 52, Hopewell Junction, NY 12533, USA. *Phone: 1-845-894-5384, wayne.zhao@globalfoundries.com, wazhao@us.ibm.com...
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Inclusion of cerium (Ce) oxide particles as an abrasive into chemical mechanical planarization (CMP) slurries has become popular for wafer fabs below the 45nm technology node due to better polishing quality and improved CMP selectivity. Transmission electron microscopy (TEM) has difficulties finding and identifying Ce-oxide residuals due to the limited region of analysis unless dedicated efforts to search for them are employed. This article presents a case study that proved the concept in which physical evidence of Ce-rich particles was directly identified by analytical TEM during a CMP tool qualification in the early stage of 20nm node technology development. This justifies the need to setup in-fab monitoring for trace amounts of CMP residuals in Si-based wafer foundries. The fact that Cr resided right above the Ce-O particle cluster, further proved that the Ce-O particles were from the wafer and not introduced during the sample preparation.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 526-531, November 11–15, 2012,
... Enhancement Methodology for Faster Yield Ramp SH Goh 1 , HC Lee 1 , TY Lim 1 , Fei Ting 1 , YT Ngow 1 , JH Ng 1 , FL Kong 1 , WY Lau 1 , SK Lim 1 , Jeffrey Lam 1 1 GLOBALFOUNDRIES, Technology Development, New Technology Prototyping, Singapore Email: gohszuhuat@globalfoundries.com Pan Yan 2 , YJ Liu 2 2...
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Scan chain integrity yield loss is a common concern, especially in early stage of product yield ramp. Typically, scan chain failure diagnosis can only proceed upon full silicon build and structural test. In this work, we propose a proactive methodology which enables failure debug step to be initiated as early as the onset of device fabrication, to bring forward yield learning. Scan chain cells and nets information are extracted from design data file and converted to inline optical wafer inspection care areas. In this way, the inspection recipe can be optimized for the detection of scan chain related defects. It is shown experimentally that such approach can potentially enhance general defect detection sensitivity by 50% and increase the defect hit probability on scan chain nets. Any findings serve as useful early data for process improvement feedback. Furthermore, marginal defects, which otherwise are not easily revealed using conventional approach, can also be detected to provide early warning for process drifts or variations.
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