Search Results for globalfoundry

A BEOL compatible Metal-Insulator-Metal capacitor (MIMCAP) was successfully developed for GlobalFoundries 14nm technology node, and subsequently introduced on customer designs as decoupling capacitors. The lead production silicon wafers with MIMCAP showed good functionality at wafer SORT functional test. However, upon testing more wafers, it became evident that the wafer center was impacted by abnormal scan logic fallout. The observed yield loss did not correlate with the MIMCAP scribe line Health Of Line (HOL) structures and the failure root cause could not be directly pin pointed to the MIMCAP process integration. Product scan diagnostic was performed and several systematic failing logical nets were identified. Subsequent failure analysis showed open via contacts in the MIMCAP vicinity. A detailed layout analysis of the FA confirmed weak-points and repeating logic nets allowed identifying a chip design topography issue resulting in a narrower process window compared to the scribe line MIMCAP HOL structure. Thanks to this knowledge the MIMCAP process was further optimized and the wafer center fallout was fully recovered in volume production.

Focused Ion Beam (FIB) circuit edit allows for rapid prototyping of potential semiconductor design changes without the need to run a full manufacturing cycle in a semiconductor Fab. By FIB editing a completed module, thorough testing on the bench or in a full system can be achieved. Logic can be toggled, validation of speed enhancements performed, and constructive and destructive failure analysis can be enabled. In order to fulfill all the needs of clients in a rapidly evolving SOC driven market, simply modifying existing devices by “rewiring” circuits is becoming insufficient. Often the team is tasked with making very repeatable structures to aid the circuit analysis group. These include relatively precise resistors for tuning RF circuits (part of an RC network), adding known loads or delays, et cetera. Naturally resistive FIB deposited metal lines connected to the existing circuitry can be used in this capacity. FIB chip edit is considered to be a “Direct Write” process. The beam pattern in conjunction with process gases defines the regions of milling and deposition. Unfortunately, FIB edit is rarely an exact science. In many cases, a number of characteristics seem to be outside the realm of precise repeatable control. This is evident not only in individual tool operational logs but also in FIB tool matching, where maintaining identical system performance within the lab is difficult or nearly impossible. These characteristics are highly dependent on precursor reservoir composition and flow, surface adsorption conditions, beam patterning integrity, and the total interaction space of competing back sputtering during the new material structure formation. Due to these factors, the shape, composition and electrical performance of metal and insulator depositions vary over an often unacceptable range. As a result, we were not meeting the needs of some critical customer applications. Direct written precision resistive structures displayed several issues for which iterative edits were required to compensate for variability. When attempting to create an exact resistance, this process was not reliable, nor was it repeatable enough for accurate circuit performance trimming. Space-constrained serpentine resistors or multiple discrete resistors side-by-side showed the greatest process variability. Metal deposition processes tend to be somewhat self-limiting, so thick boxprofile lines are difficult to form. Conductive material deposited outside of the pattern definition (overspray) results in line-to-line leakages. Attempts to remove the overspray thru ion beam assisted etch-back tends to damage the deposited conductors and underlying insulators. The low-k region between lines can become cross-linked, experience gallium doping, and become tungsten impregnated. This lowered the resistivity of the insulator, increased the resistivity of the conductor, and produced variability in the device which was especially an issue when dealing with varying initial substrates. GLOBALFOUNDRIES began a project to create a more robust repeatable resistive structure by removing several variables. Rather than direct writing lines onto a top surface layer, a confined deposition based on the concepts of dual damascene processing used with copper layers in modern semiconductor fabrication will be employed. The damascene process begins with the definition of a box to be filled with a conductive material. The process of ion beam gas assisted anisotropic etching/milling has a far more predictable outcome than ion beam induced deposition. It is possible to create a surface box mill or even a deep drilled via of desired dimensions with a more consistent repeatability. Deposition of tungsten into a confined region using, for example, a W(CO)6 precursor and a Ga+ ion beam results in an excellent via fill. Using this behavior, precision resistors can be created with metal deposition within the trenches which are created by the gas assisted mill. An enclosed space can be filled nearly void-free, and has repeatable electrical parameters. The self-limiting factors with tungsten deposition go away as sputtered material becomes trapped within the well resulting in a near limitless Zheight potential. The constant dielectric with a uniform and contained tungsten fill can allow for a well-defined resistivity for the FIB deposited tungsten material. Having a known resistivity, calculation of dimensions for resistive and inductive structures during the design process becomes feasible. With process variability under control, structures can be formed reliably enough to offer this as a service to customers.

Listings of the EDFAS 2019-2020 Board of Directors and ISTFA 2019 Organizing Committee, Activities Chairs, and Technical Program Committee.

Listings of the EDFAS 2017-2018 Board of Directors, the ISTFA 2017 Organizing Committee and Activities Chairs, and other contributors and committee members.

Listings of the EDFAS 2016-2017 Board of Directors, the ISTFA 2016 Organizing Committee and Activities Chairs, and other contributors and committee members.

Listings of the EDFAS 2015-2016 Board of Directors, the ISTFA 2015 Organizing Committee and Activities Chairs, and other contributors and committee members.

Listings of the EDFAS 2017-2018 Board of Directors, the ISTFA 2017 Organizing Committee and Activities Chairs, and other contributors and committee members.

Listings of the EDFAS 2022 Board of Directors and the ISTFA 2022 Organizing Committee and Session Chairs.

Listings of the EDFAS 2022 Board of Directors and the ISTFA 2022 Organizing Committee and Session Chairs.

Listings of the EDFAS 2024 Board of Directors and the ISTFA 2024 Organizing Committee and Session Chairs.

Listings of the EDFAS 2024 Board of Directors and the ISTFA 2024 Organizing Committee and Session Chairs.

Listings of the EDFAS 2021-2022 Board of Directors and ISTFA 2021 Organizing Committee and Session Chairs.

Listings of the EDFAS 2021-2022 Board of Directors and ISTFA 2021 Organizing Committee and Session Chairs.

Listings of the EDFAS 2020-2021 Board of Directors and EDFAS 2020 Virtual Workshop Organizing Committee and Activities Chairs.

Listings of the EDFAS 2023 Board of Directors and the ISTFA 2023 Organizing Committee and Session Chairs.

Listings of the EDFAS 2023 Board of Directors and the ISTFA 2023 Organizing Committee and Session Chairs.

Through inline processing of a prospective Spin on Hardmask (SOH) material, bubble defects were observed randomly across a wafer. Several complementary FA techniques were utilized to characterize the bubble defects including SEM, TEM, and chemical analysis techniques. The root cause of defect formation was identified as a raw material imperfection in SOH, which led to excessive outgassing. Imperfections within the substrate formed nucleation sites for outgassing of SOH material forming bubbles, which allowed voids to propagate. These findings led to implementation of greater quality control methods by the raw material manufacturer.

As the rapid developments of semiconductor manufacturing technologies, the CD of the device keep shrinking. The IC devices have a smaller feature sizes and higher densities, and thus there are many challenges come up in terms of the failure analysis and localized device characterization. Besides the challenge of smaller feature size, there is another challenge as well. Some of the traditional FA method can no longer be employed on advanced technologies, such as 28nm and beyond. Quickly and successfully isolating the failed location and obtaining electrical signature of the defect has become more of a challenge, especially for the device level analysis and characterization. AFP nanoprobing system provides some solutions to advanced nodes fault isolation through its AFM imaging mode of CAFM.

Through custom test pattern generation and SRAM design analysis, we present the first demonstration of Laser Voltage Imaging (LVI) and Probing (LVP) for the successful fault isolation and physical analysis of DQ failures within a 14nm SRAM macro. These findings revealed the fail site to reside within the I/O circuitry of the associated failing pin, a previously overlooked location as common block failures are typically associated with physical anomalies within the SRAM periphery.

This work presents a novel method of continuous improvement for faster, better and cheaper TEM sample preparation using Cut Look and Measure (CLM). The improvement of the process is executed by operational monitoring of daily beam conditions, end products, bulk thickness control, recipe usage and tool running time. This process produces a consequent decrease in rework rate and process time. In addition, it also increases throughput with better quality TEM samples.