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flip-flops

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Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 180-187, November 2–6, 2008,
... to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 93-103, October 28–November 1, 2018,
... state of flip flops in a scan chain. Results are also presented to establish that LIFA can be configured as a hardware-based diagnostics platform. 25 ps 1064 nm diode laser laser-induced fault analysis scan chain fault isolation single event upsets Scan Chain Fault Isolation using Single...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 384-390, November 2–6, 2003,
.... Analysis of failing devices, however, becomes more complex as scan chains contain a large number of flip flops and localization of the failing net is a prerequisite for subsequent physical failure analysis (PFA). This becomes especially true for flip chip products, since access to the chip front side...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 334-336, October 31–November 4, 2021,
...Abstract Abstract This paper presents an alternative approach for analyzing complex scan chain failures in which there are multiple candidates that could be the root cause. It demonstrates the approach on an automotive IC with several failing flip-flops. An analysis of the interconnections...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 366-368, October 31–November 4, 2021,
... flip-flop) was narrowed down to a few chain links and ultimately pinpointed using EOP fault isolation techniques. The failed device was then deprocessed by parallel lapping and analyzed in a SEM, revealing a broken poly gate as the physical cause of failure. electrical fault isolation electro...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 396-401, November 2–6, 2008,
... and to measure timing slack on sub-nets in the failing circuitry. This allows very close correlation between timing models and silicon performance leading to more robust design/process matching. Introduction Scan test is based on the use of chained flip-flops to stimulate and observe specific patterns...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 280-289, October 28–November 1, 2018,
... probing attacks are memory cells, registers, and PUFs that process sensitive data, e.g. secret keys. As PEM attacks are more challenging on scaled-down CMOS devices, we focus our discussion on LVP attacks. Here, we consider an LVP attack on an 8-bit register based on D- type flip-flops (FFs) as a running...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 323-329, November 11–15, 2001,
... to a reference. The root cause of the high resistance is a void in the stacked via of the bitline contact. A FIB cross-section is shown in fig. 6 (b). Single Cell Failure A single port six transistor SRAM cell can be divided into two base structures: 1. a flip-flop and 2. two access transistors. The toggle state...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 415-418, November 10–14, 2019,
... the failure to specific flip flops. Physical failure analysis (PFA) revealed a broken segment of polysilicon. These failures were also observed to be bake recoverable, explaining how these devices were tested as good units during production. The challenge was to find a way to effectively screen these devices...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 18-23, November 13–17, 2011,
... signal called scan enable is added to a design. When this signal is asserted, every flip-flop (FF) in the design is connected into a long shift register, one input pin provides the data to this chain, and one output pin is connected to the output of the chain. In this scan mode, using the chip clock...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 128-134, November 6–10, 2005,
... preparation of the devices and some time to search the failed flip-flop (FF) in the scan chain and the affected FET in the FF. Another localization method is soft defect localization (SDL) [4-5], which will be discussed below in detail. In this paper, a new localization method, named Lock-In Assisted Soft...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 409-413, November 14–18, 2004,
... test Interconnects under test Interconnects under test Interconnects under test Interconnects under test Interconnects under test Figure 3: Sample of metal interconnects defect monitoring test pattern. The interconnect type under test is used to connect the flip- flops. The flip-flops used...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 261-263, November 15–19, 2020,
...: 10.31399/asm.cp.istfa2020p0261 Fig. 2: Representation of nets highlighted by PEM analysis: the violet net is connected to several combinatory logic ports, the cyan net corresponds to the reset input signal shared between several flip-flops. In yellow (transition fault model) and red (stuck-at fault model...
Proceedings Papers

ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 193-197, November 15–19, 2009,
... reduced the analysis time. The cells in the data path consist of both D flip-flops and buffers. Wherever possible signal acquisition was taken at a buffer due to its relatively large size and its strong modulation of the LVP s probing laser. However, as the binary search narrows, there may...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 153-157, November 13–17, 2011,
... stream in the first flip flop of the serial register (SCAN IN) and we expect to detect the same data stream at the output of the last flip flop (SCAN OUT). In our case, the SCAN OUT information was always stuck at 1 and the EDA diagnosis tool did not give any useful prediction. It just classified...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 380-384, November 14–18, 2004,
... in the downstream gate. Stuck open faults Gate oxide shorts Most stuck at faults Latch up Delay faults Any other faults due to extra conductor, missing isolating layer, excess well/substrate leakage. LED integrated with IC module (ICM) ICM is a LED display integrated with driver. Two D-type flip- flop...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 228-237, November 5–9, 2017,
.... In addition to the LADA sites discussed above, TR-LADA images highlighted the presence of highly-defined sites not part of the path of the transition, but drive the transition path with static inputs. We call these static path sites (SPS) to differentiate them from the flip-flop upsets that are unrelated...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 91-97, November 13–17, 2011,
... a sensitivity of the failures at the center of the wafer to a certain type of flip-flop cell, FF-Type-A, failing as a Stuck-at-1. A stacked wafermap of devices that contain FF-Type-A in their diagnosis result is shown in Figure 3a. Figure 3b shows the stacked wafermap when the devices that contain...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 176-181, November 13–17, 2011,
.../chip.lvdb.Manufacturing LVDB Name: chip.lvdb.Manufacturing Test Config: chip TestStep: pmmu7_lbist (FAILED) LogicController "BP42" (p_clk, 5ns) Number of failing trials = 744( 1 2 3 7 8 10 15 20 23 24 27 30 31 32 33 40 41 42 43 .. 1024) Trial "1" has failing flip-flop instances in collar instance "pmmu7...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 82-86, November 9–13, 2014,
... laser pulse was synchronized at the specified time relative to the beginning of the test loop. The direction of propagation of the critical signal is evident by recording the time each site disappears. The small sites in the circled area are flip flop single-event upsets [7], unrelated to the path...