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flip-chips

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Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 275-280, November 11–15, 2001,
...Abstract Abstract Results of experimental studies are presented which address a concern that gallium staining from FIB imaging during backside editing might degrade IR navigation as well as signal acquisition during probing of flip chips by such techniques as Picosecond Imaging Circuit Analysis...
Proceedings Papers

ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 455-459, November 15–19, 1998,
...Abstract Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 118-124, November 6–10, 2016,
...Abstract Abstract This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 635-637, November 6–10, 2016,
... be examined to evaluate the risks for possible field failures of this defect. contamination copper pillar bumps failure analysis flip chip packages silicon solders surface roughness wettability Non-wetting effects of Si contamination on Cu bumps of a flip chip package: A Case Study Janella Mae...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 191-195, October 28–November 1, 2018,
...Abstract Abstract We report the results of our studies on thermally induced surface topography changes in ultra-thinned silicon flip-chip packaged devices. Previous results showed that over polishing can result in bump topography on the ultra-thinned Si backside. The topographic bumps were...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 505-509, October 28–November 1, 2018,
...Abstract Abstract Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 239-242, November 12–16, 2006,
...Abstract Abstract The present paper is a study on flip-chip open bump failure mechanism. Initial electrical testing showed open circuit condition. Scanning acoustic microscope (C-SAM) identifies delamination on particular bump(s). Initial cross-sectional images suggested that the separation...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 77-80, November 4–8, 2007,
...Abstract Abstract By implementing two-photon optical-beam-induced current microscopy using a solid-immersion lens, imaging inside a silicon flip chip is reported with 166nm lateral resolution and an axial resolution capable of resolving features only 100nm in height. failure analysis...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 36-42, November 2–6, 2008,
...Abstract Abstract The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 81-85, November 13–17, 2011,
...Abstract Abstract This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 21-25, November 11–15, 2012,
... for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 197-202, November 11–15, 2012,
... and faults in failing IC devices. The case studies illustrate the applications of the method for 28nm flip chip bulk Si CMOS devices and demonstrate how it is used in providing insight into the fab process and design for process and yield improvements. The methods are expected to play an even more important...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 316-324, November 11–15, 2012,
...Abstract Abstract This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation...
Proceedings Papers

ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 485-490, November 11–15, 2012,
...Abstract Abstract In this paper we will discuss an empirically discovered technique to remove residual solder bumps or remnants using reflow and wicking to a gold plated surface rather than mechanical or chemical means. Extraction of flip chip ICs, for the purpose of repackaging, can leave bond...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 1-6, November 3–7, 2013,
... reflectometry (TDR), scanning SQUID SDR provides a truly two-dimensional physical image of device under test with spatial resolution down to 30 μm [1]. In this paper, the SQUID SDR technique is used to isolate dead open faults in flip-chip devices. The experimental results demonstrate the capability of SDR...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 264-269, November 3–7, 2013,
...Abstract Abstract Electro Optical Terahertz Pulse Reflectometry (EOTPR), a terahertz based Time Domain Reflectometry (TDR) technique, has been evaluated on Flip Chip (FC) and 3D packages. The reduced size and complexity of these new generations of advanced IC products necessitate non...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 501-504, November 3–7, 2013,
...-processing requires mechanical grinding to thin down the silicon thickness before wet etching. This paper introduces an effective way by skipping mechanical grinding and by etching at high temperature in case of thin flip chip. The backside silicon images are presented and compared after de-processing...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 553-559, November 3–7, 2013,
...Abstract Abstract Mechanical thinning of Si die backside was introduced to support fault isolation for flip chip package in this paper. The backside milling system provides two types of thinning with good die planarity and mirror polishing to yield a high image quality for fault isolation...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 73-81, November 14–18, 2004,
... for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 633-635, November 14–18, 2004,
...Abstract Abstract Chip access for flip-chip packages in high-performance microprocessors is performed by removing the lid then by extraction of the die from the package substrate. Residual stresses built in temperature cycled (TC) units result in a low success rate using conventional delidding...