Abstract Results of experimental studies are presented which address a concern that gallium staining from FIB imaging during backside editing might degrade IR navigation as well as signal acquisition during probing of flip chips by such techniques as Picosecond Imaging Circuit Analysis (PICA) and Laser Voltage Probing (LVP). Although optical transparency does depend on gallium implantation dose, Ga staining is, however, not necessarily a limitation to the implementation of photon optical tools in the debug laboratory. Comparisons are made on the results from devices under the following conditions: with and without an anti-reflective (AR) coating, with and without XeF2 enhancement during FIB etching, and with confocal laser scanning microscope (CLSM) imaging and CCD-based IR microscope imaging.

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of traditional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its electron device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology offers access to diagnosing failures in flip-chip assembled parts.

Abstract In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.

Abstract Two novel techniques to identify continuity failures in multi-layer substrates of flip-chip package are discussed. The first technique uses the custom designed and fabricated Package Substrate Probe Fixture (PSPF™). The fixture eliminates the traditional method of soldering directly to the package solder balls. This ensures that failures are not heat cured and the solder ball as well as the Ball Grid Array (BGA) pad are not detached from the package substrate during physical analysis. Also employed are beam-based systems that include both Focused Ion Beam (FIB) and Electron-beam (Ebeam) to detect Capacitive Coupling Voltage Contrast (CCVC) images. Voltage contrast imaging augments traditional optical inspection techniques using bright and dark field microscopy.

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Abstract Solder bumps are frequently the sites of defects that cause continuity failures in ceramic flip chip packages. In concurrent technology the solder bump is a multi-layered structure containing several interfaces. Conventional c-SAM imaging alone cannot delineate subtle bump defects. In this article we present experimental results that document the nature of interface defects in multi-layered solder bumps as well as their acoustic signatures. The acoustic signatures obtained from defective bumps are contrasted with the signals obtained from pristine bumps and the sensitive nature of these signatures to defects is highlighted.

Abstract In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap. This inherent wavelength limitation, together with the shrinking dimensions of modern CMOS devices, limit the capabilities of these tools. It is known that the optical resolution limits of the LVP and TRLEM techniques are bounded by the diffraction limit which is ~1um for both tools using standard optics. This limitation was reduced with the addition of immersion lens optics. Nevertheless, even with this improvement, shrinking transistor geometry is leading to increased acquisition time, and the overlapping effect between adjacent nodes remains a critical issue. The resolution limit is an order of magnitude above the device feature densities in the < 90nm era. The scaling down of transistor geometry is leading to the inevitable consequence where more than 50% of the transistors in 90nm process have widths smaller than 0.4um. The acquisition time of such nodes becomes unreasonably long. In order to examine nodes in a dense logic cuicuit, cross talk and convolution effects between neighboring signals also need to be considered. In this paper we will demonstrate the impact that these effects may have on modern design. In order to maintain the debug capability, with the currently available analytical tools for future technologies, conceptual modification of the FA process is required. This process should start on the IC design board where the VLSI designer should be familiar with FA constraints, and thus apply features that will enable enhanced FA capabilities to the circuit in hand during the electrical design or during the physical design stages. The necessity for reliable failure analysis in real-time should dictate that the designer of advanced VLSI blocks incorporates failure analysis constraints among other design rules. The purpose of this research is to supply the scientific basis for the optimal incorporation of design rules for optical probing in the < 90nm gate era. Circuit designers are usually familiar with the nodes in the design which are critical for debug, and the type of measurement (logic or DC level) they require. The designer should enable the measurement of these signals by applying certain circuit and physical constraints. The implementation of these constraints may be done at the cell level, the block level or during the integration. We will discuss the solutions, which should be considered in order to mitigate tool limitations, and also to enable their use for next generation processes.

Abstract The present paper is a study on flip-chip open bump failure mechanism. Initial electrical testing showed open circuit condition. Scanning acoustic microscope (C-SAM) identifies delamination on particular bump(s). Initial cross-sectional images suggested that the separation took place at Al – TiW interface. However, EDS analysis on the separated surface indicated the presence of Al metal at both sides of the separation, which raises a question of why the Al layer is cracked or separated instead of interface de-lamination. Research in literature and investigation at assembly line points an ultrasonic cleaning step in manufacturing process as a contributor to the open bump failure. Examining virgin dice after bump removal observed crack in nitride passivation around the bump neck, indicating high stress level during passivation film deposition and/or bump formation process. Hence it is concluded that ultrasonic cleaning in device assembly aggravates preexisting stress in weak bump(s), resulting in latent failure in field application.

Abstract By implementing two-photon optical-beam-induced current microscopy using a solid-immersion lens, imaging inside a silicon flip chip is reported with 166nm lateral resolution and an axial resolution capable of resolving features only 100nm in height.

Abstract The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

Abstract This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.

Abstract Chip access for flip-chip packages in high-performance microprocessors is performed by removing the lid then by extraction of the die from the package substrate. Residual stresses built in temperature cycled (TC) units result in a low success rate using conventional delidding techniques. A need has developed in failure analysis for stress-free removal of the materials surrounding a flip-chip device. This paper discusses a novel, cost effective, wet chemical process that has been developed for thin die and lid removal of flip-chip packaged units. The process uses n-methy-2-pyrrolidone (NMP) for epoxy-based lid attach and underfill materials. A reflux unit is designed to reduce the risk of fire and explosion when the sample is heated in the solvent to the desired temperature. The method of heating reduces the chance of thermal shock, which could fracture the sample due to rapid heating or cooling.

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

Abstract Scanning acoustic microscopy (SAM) is a non-destructive tool for analysis of packaged devices. New materials, package configurations, and technologies have required adaptation of standard practices in SAM. The detection of cracked die, voids, or delamination in the underfill or package are standard issues for SAM. SAM can routinely detect large cracks through the central 80% of the die; however, the occurrence of smaller cracks at the edge of the flip chip die is problematic. This article proposes a model in which alteration in the standard SAM parameters, the gain and Time-of-Flight, enable detection of die edge cracks in assembled Flip Chip devices. IR imaging after thinning and polishing of the die confirms the die edge cracks. The SAM analysis can replace the IR imaging for detection of small die edge cracks taking minutes to complete instead of the hours involved in the sample preparation for IR imaging.

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

Abstract The increasing popularity of flip-chips brings new challenges to those who must perform device analysis (1). Its ability to accommodate high pin-count and high bandwidth microprocessors, DSPs and complex logic devices is increasing the demand for this technology. Conventional e-beam and mechanical probing techniques currently allow quick and efficient analysis of conventional semiconductor devices. When the surface of the device is not exposed, however, conventional analysis techniques are insufficient and new techniques must be developed. Conventional packaging technologies allow design debug and failure analysis to be performed in a relatively straightforward manner. Analysis from the topside is clearly the preferred technique when possible (2), using specially prepared engineering prototypes, but backside access for dynamic timing analysis is required when topside techniques are exhausted. The flipchip process, however, makes topside analysis impractical in most situations. There are several different techniques that are currently being used for backside analysis. These are emission microscopy (3), optical beam induced current (OBIC) (4), and a combination of software and built in self-test/scan methods (5). These techniques are valuable in helping engineers to analyze and isolate faults for functional failures. These techniques do not, however, provide precise analog waveforms which may be used to perform timing analysis on the device. A backside pulsed laser electro-optic technique for measuring internal node timing (6) has been developed for waveform acquisition. Although this technique permits acquisition of waveforms from a bi-polar device which has had its substrate thinned, it has limited application to CMOS devices, particularly in long duty cycle applications. Milling the backside of devices in order to facilitate backside waveform acquisition is considered by some researchers as a potential approach, but the authors are not aware of any published data on this subject.

Abstract Laser microchemical (LMC) technology has become an important element of the FIA and debug tool set by supplying key steps not well addressed by previous tools. In this paper we report the optimization of the LMC technology to solve key issues for flip chip FIA. Specific processes have been developed for localized thinning of flip chips, in order to enable access of conventional FIA tools. Additional applications include dramatic enhancement of focused ion beam (FIB) rework and 3-D micromachining for prototyping, in-situ trimming, and mastering of microelectromechanical systems (MEMS). Laser etching of silicon is with a high pressure chlorine assist and is l000X the rate of the fastest focused ion beam methods. In contrast to grinding methods, the process introduces no process stress or contamination and retains an average surface roughness of several hundred angstroms. Micronthickness metal lines are laid down in a one-step vapor phase deposition at 200 μm/s writing speed. Rapid deposition combined with the superior quality of the laser interconnect, translates into writing with a conductance per unit writing time of 1000 to 10,000 times the rate of a focused ion beam.

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.