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flip chips

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Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 275-280, November 11–15, 2001,
...Abstract Abstract Results of experimental studies are presented which address a concern that gallium staining from FIB imaging during backside editing might degrade IR navigation as well as signal acquisition during probing of flip chips by such techniques as Picosecond Imaging Circuit Analysis...
Proceedings Papers

ISTFA1998, ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis, 455-459, November 15–19, 1998,
...Abstract Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 69-76, November 11–15, 2001,
... and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flip- chip assemblies. In this paper, the application of SQUID microscope in resolving multiple failure modes will be presented. Examples include use of SQUID...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 243-250, November 11–15, 2001,
...Abstract Abstract Two novel techniques to identify continuity failures in multi-layer substrates of flip-chip package are discussed. The first technique uses the custom designed and fabricated Package Substrate Probe Fixture (PSPF™). The fixture eliminates the traditional method of soldering...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 189-193, November 3–7, 2002,
...Abstract Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 683-687, November 3–7, 2002,
...Abstract Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 68-75, November 2–6, 2003,
...Abstract Abstract Solder bumps are frequently the sites of defects that cause continuity failures in ceramic flip chip packages. In concurrent technology the solder bump is a multi-layered structure containing several interfaces. Conventional c-SAM imaging alone cannot delineate subtle bump...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 184-190, November 2–6, 2003,
...Abstract Abstract In recent years, two new techniques were introduced for flip chip debug; the Laser Voltage Probing (LVP) technique and Time Resolved Light Emission Microscopy (TRLEM). Both techniques utilize the silicon’s relative transparency to wavelengths longer than the band gap...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 239-242, November 12–16, 2006,
...Abstract Abstract The present paper is a study on flip-chip open bump failure mechanism. Initial electrical testing showed open circuit condition. Scanning acoustic microscope (C-SAM) identifies delamination on particular bump(s). Initial cross-sectional images suggested that the separation...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 77-80, November 4–8, 2007,
...Abstract Abstract By implementing two-photon optical-beam-induced current microscopy using a solid-immersion lens, imaging inside a silicon flip chip is reported with 166nm lateral resolution and an axial resolution capable of resolving features only 100nm in height. failure analysis...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 36-42, November 2–6, 2008,
...Abstract Abstract The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 81-85, November 13–17, 2011,
...Abstract Abstract This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 73-81, November 14–18, 2004,
... for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 633-635, November 14–18, 2004,
...Abstract Abstract Chip access for flip-chip packages in high-performance microprocessors is performed by removing the lid then by extraction of the die from the package substrate. Residual stresses built in temperature cycled (TC) units result in a low success rate using conventional delidding...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 669-672, November 14–18, 2004,
...Abstract Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 199-201, November 6–10, 2005,
... or package are standard issues for SAM. SAM can routinely detect large cracks through the central 80% of the die; however, the occurrence of smaller cracks at the edge of the flip chip die is problematic. This article proposes a model in which alteration in the standard SAM parameters, the gain and Time...
Proceedings Papers

ISTFA1996, ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis, 277-283, November 18–22, 1996,
...Abstract Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI...
Proceedings Papers

ISTFA1996, ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis, 381-386, November 18–22, 1996,
...Abstract Abstract The increasing popularity of flip-chips brings new challenges to those who must perform device analysis (1). Its ability to accommodate high pin-count and high bandwidth microprocessors, DSPs and complex logic devices is increasing the demand for this technology. Conventional...
Proceedings Papers

ISTFA1997, ISTFA 1997: Conference Proceedings from the 23rd International Symposium for Testing and Failure Analysis, 211-213, October 27–31, 1997,
...Abstract Abstract Laser microchemical (LMC) technology has become an important element of the FIA and debug tool set by supplying key steps not well addressed by previous tools. In this paper we report the optimization of the LMC technology to solve key issues for flip chip FIA. Specific...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 100-104, November 9–13, 2014,
...Abstract Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure...