Abstract This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.

Abstract For 22nm technology node and beyond, fully depleted devices such as FinFET and ETSOI are leading candidates. Certain critical dimensions of such devices are well below 10nm, and only transmission electron microscopy (TEM) has the resolution to provide measurement with sub-nanometer accuracy. Due to the projection effect of TEM technique, comprehensive understanding of the 3D structure from 2D images is needed for process development of FinFET. This paper will address sample preparations and TEM imaging techniques for FinFET device at sub-100nm pitch.

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

Abstract We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

Abstract The potential benefits and challenges of low kV SEM imaging and EDS elemental analysis have been discussed in the SEM community since at least the early 1990s [1,2]. Concurrent with steady progress in the performance of so-called extreme high-resolution ‘XHR’ SEM imaging [3], is an advancement in low-energy EDS using windowless, large solid angle ‘racetrack’ EDS detectors [4]. As lower kV imaging and EDS analysis becomes accessible, refined models of the interaction of low energy electron beam and real-world samples continues at full speed even today [5].

Abstract In this paper, the stacking fault defects in FinFETs are described as the root cause of the PLL failure. Failure analysis approaches such as photon emission microscopy and nano probing were applied to pinpoint the exact stacking fault location in even transistor level and High resolution TEM confirmed the stacking fault defects in the Fin which was isolated by nano probing. RX local density was confirmed as the key factor in stacking fault generation by TCAD simulation. RX new mask with dummy addition was made to mitigate stress and was confirmed to be effective to reduce the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices. Keywords – Stacking Fault, Geometric Phase Analysis

Abstract This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

Abstract Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

Abstract This paper demonstrates a two-pin Electron Beam Induced Current (EBIC) isolation technique to isolate the defective Fin with gate oxide damage in advanced Fin Field Effect Transistor (FinFET) devices. The basic principle of this twopin configuration is similar to two-point Electron Beam Absorption Current (EBAC) technique: a second pin as ground on the gate is added to partially shunt the EBIC current and thus creates EBIC contrast from the defective Fin. In this way, the challenge of highly resistive short path inside the Fin in a narrow gate can be overcome. The paper will provide failure analysis details using this technique for defective Fin isolation.

Abstract New heterogeneous 3D integration schemes and continuing miniaturization of semiconductor packaging components, such as micropillars, are driving demand for substantive changes to conventional PFA (physical failure analysis). In particular, desired performance capabilities include the ability to nondestructively determine failures within seconds to minutes. New tools should be quantitative, have sufficient resolution to determine sub-micron sized defects and voids in TSVs at the wafer or package level. It should also measure thickness and their material composition of multilayer structures above the wafer surface, such as microbumps, or those below the surface including UBM and RDL. In this paper we are introducing a novel x-ray fluorescence microscope technique capable of solving the above applications in advanced packaging for PFA and process development. The same technique can also be applied in the front end metrology of new gate materials, 3D FinFET structures within test structures in patterned wafers. Characterization of sub nanoscopic changes (sensitivity of sub-angstrom) in film and dopants deposited in 3D structures will also be shown. With its high sensitivity for trace materials, contamination analysis of post hard mask residue, post metal etch residue especially in high aspect ratio structures is also possible.

Abstract Infrared optical probing techniques that have significant applications to and continued development for silicon physical debug have existed for decades. More recently, resolution enhancement achieved by improving numerical aperture, etc. have reached fundamental limits and the ability for resolution to match node scaling with radiation transparent to silicon (photon energy < silicon bandgap) becomes diffraction limited for some 10nm and many future process nodes. Decreasing the wavelength used for imaging and signal acquisition can improve resolution; however, it is well documented that absorption increases sharply for photons with energy greater than the bandgap of the bulk substrate material. Significant reduction in the thickness of the backside substrate material can be performed to achieve acceptable transmission through the absorbing substrate, but the requirement for very thin sample preparation significantly modifies the thermal system surrounding active circuitry. Here, high aspect ratio trenches are shown to offer a unique method to take advantage of thick silicon (> 100µm) for lateral heat dissipation as well as thin silicon (< 2µm) for minimally absorbing optical path in close proximity to enable case-by-case preparation methods for postsilicon labs faced with visible light resolution requirements on high power density circuits.

Abstract In 1986 the Atomic Force Microscope (AFM) was invented by Gerd Binnig, Christoph Gerber, and Calvin Quate [1]. Since then, numerous analytical techniques have been developed and implemented on the AFM platform, evolving into what is collectively called the Scanning Probe Microscope (SPM). The SPM has since become well established as a mainstream analytical instrument with a continually increasing role in the development of nanoscale semiconductor technologies providing critical data from initial concept to technology development to manufacturing to failure analysis [2]. Scanning Capacitance Microscopy (SCM) has a longstanding, well-established track record for detecting dopant-related mechanisms that adversely affect device performance on planar (Field Effect Transistor) FETs as well as other structures (e.g., diodes, capacitors, resistors). The semiconductor industry’s transition to three dimensional FinFET devices has resulted in many challenges with regard to device analysis. This is especially true when it is necessary to perform detailed dopant analysis on a specific device; the device may be comprised of a single or multiple fins that have been called out specifically through traditional fault localization techniques. Scanning Capacitance Spectroscopy (SCS) is an analytical method, implemented on the SCM platform in which a series of DC bias conditions is applied to the sample and the carrier response is recorded using SCM [3]. SCS has a proven history of highlighting dopant related anomalies in semiconductor devices, which, in some instances, might not otherwise be “visible”. This paper describes successful application of SCM and SCS in showing, in full detail, a dopant-related failure mechanism on an individual, location-specific 14 nm FinFET.

Abstract The FinFET has been introduced in the last decade to provide better transistor performance as the device size shrinks. The performance of FinFET is highly sensitive to the size and shape of the fin, which needs to be optimized with tighter control. Manual measurement of nano-scale features on TEM images of FinFET is not only a time consuming and tedious task, but also prone to error owing to visual judgment. Here, an auto-metrology approach is presented to extract the measured values with higher precision and accuracy so that the uncertainty in the manual measurement can be minimized. Firstly, a FinFET TEM image is processed through an edge detecting algorithm to reveal the fin profile precisely. Finally, an algorithm is utilized to calculate out the required geometrical data relevant to the FinFET parameters and summarizes them to a table or plots a graph based on the purpose of data interpretation. This auto-metrology approach is expected to be adopted by academia and/or industry for proper data analysis and interpretation with higher precision and efficiency.

Abstract With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

Abstract As semiconductor device scaling continues to reduce the structure size, device geometries are also changing to three dimensional structures such as finFETs, and the materials which compose the devices are also evolving to obtain additional device performance gains. The material change studied in this paper is the introduction of silicon germanium into the electrically active region of a finFET test structure. The paper demonstrates a quantitative energy dispersive X-ray spectroscopy transmission electron microscopy (TEM) technique through the use of blanket film calibration samples of known concentration characterized by X-ray diffraction. The technique is used to identify a test structure issue which could only be diagnosed with a technique having nanometer spatial resolution and atomic percent sensitivity. The results of the test structure analysis are independently verified by the complementary TEM electron energy loss spectroscopy technique.

Abstract In the case of conventional planar FET, Dynamic Laser Stimulation (DLS) is a very effective method to isolate marginal failure. Depending on laser sources, DLS is divided by Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). SDL uses 1320nm wavelength laser source in order to induce localized heat. On the other hand, LADA uses 1064nm wavelength laser source to generate photo carriers. But for the FinFET the effect of laser stimulation is not clear yet. This paper introduces the effect of laser stimulation on FinFET transistors based on wavelength, the so called LADA and two-photon LADA. The experimental data show changes in Vth and Idsat with different character for a single FinFET transistor. A case study further explains this laser stimulation effect via scan chain LVcc marginal failure analysis localized with 1320nm CW laser stimulation and nano-probing analysis.

Abstract The result of applying normal xenon ion beam milling combined with patented DX chemistry to delayer state-of-theart commercial-grade 14nm finFETs has been demonstrated in a Helios Plasma FIB DualBeam™. AFM, Conductive-AFM and nano-probing with the Hyperion Atomic Force nanoProber™ were used to confirm the capability of the Helios PFIB DualBeam to delayer samples from metal-6 down to metal-0/local interconnect layer and in under two hours produce a sample that is compatible with the fault isolation, redetection, and characterization capabilities of the AFP. IV (current-voltage) curves were obtained from representative metal-0 contacts exposed by the PFIB+DX delayering process and no degradation to device parameters was uncovered in the experiments that were run. Compared to mechanically delayering samples, the many benefits of using the PFIB+DX process to delayer samples for nano-probing were conclusively demonstrated. Such benefits, include sitespecificity, precise control over the amount of material removed, >100μm square DUT (device under test) area, nm-scale flatness over the DUT area, nm-scale topography between contacts and the surrounding ILD, uniform conductivity across the DUT area, all with no obvious detrimental effects on typical DC device parameters measured by nano-probing.

Abstract In a previous study, the authors introduced a novel technique of using low-beam energy Gallium Focused Ion Beam to expose a large area of Shallow Trench Isolation (STI) over a Dynamic Ring Oscillator (DRO) incurring virtually no change of its operating frequency. In this paper, the authors further investigate the influence of extended dose delivery of 5 kV Ga+ after the initial exposure of the STI over a DRO on modern 7 nm process. The motivation of this study is to understand the dynamics between the Ga+ ion interaction at lower beam energies on live and functional devices and the failure mechanism of the device from such interaction. The frequency of the DROs after the initial STI exposure at 5 kV exhibits <1% increase. Additional dosage of lowkV exposure was performed over the exposed STI and its effects on the DRO frequency was monitored. Finally TEM analysis of the irradiated DROs will be analyzed to understand the failure mechanism of transistors.

Abstract Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

Abstract Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.