This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.

Electrooptical investigations such as laser voltage probing (LVP) and dynamic laser stimulation (DLS) are very popular electrical fault isolation techniques (EFI) that use lasers on semiconductor circuits to study the functionality of transistors while the device is in operation. While many studies have been undertaken to understand interaction between laser and planar devices, three-dimensional devices such as FinFETs have interesting physiologies that have not been fully explored. In this work, we study the interaction of polarized light with the n-type metal oxide semiconductor (NMOS) FinFETs, experimentally and through Multiphysics simulations. We report highly directional electrooptical interactions in the FinFET. LVP signals are stronger when the laser used is polarized parallel to the fin and laser stimulation stronger when the laser used is polarized parallel to the gate. These findings affect future laser stimulation and probing investigations for EFI.

Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

The potential benefits and challenges of low kV SEM imaging and EDS elemental analysis have been discussed in the SEM community since at least the early 1990s [1,2]. Concurrent with steady progress in the performance of so-called extreme high-resolution ‘XHR’ SEM imaging [3], is an advancement in low-energy EDS using windowless, large solid angle ‘racetrack’ EDS detectors [4]. As lower kV imaging and EDS analysis becomes accessible, refined models of the interaction of low energy electron beam and real-world samples continues at full speed even today [5].

In this paper, the stacking fault defects in FinFETs are described as the root cause of the PLL failure. Failure analysis approaches such as photon emission microscopy and nano probing were applied to pinpoint the exact stacking fault location in even transistor level and High resolution TEM confirmed the stacking fault defects in the Fin which was isolated by nano probing. RX local density was confirmed as the key factor in stacking fault generation by TCAD simulation. RX new mask with dummy addition was made to mitigate stress and was confirmed to be effective to reduce the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices. Keywords – Stacking Fault, Geometric Phase Analysis

This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

This paper demonstrates a two-pin Electron Beam Induced Current (EBIC) isolation technique to isolate the defective Fin with gate oxide damage in advanced Fin Field Effect Transistor (FinFET) devices. The basic principle of this twopin configuration is similar to two-point Electron Beam Absorption Current (EBAC) technique: a second pin as ground on the gate is added to partially shunt the EBIC current and thus creates EBIC contrast from the defective Fin. In this way, the challenge of highly resistive short path inside the Fin in a narrow gate can be overcome. The paper will provide failure analysis details using this technique for defective Fin isolation.

New heterogeneous 3D integration schemes and continuing miniaturization of semiconductor packaging components, such as micropillars, are driving demand for substantive changes to conventional PFA (physical failure analysis). In particular, desired performance capabilities include the ability to nondestructively determine failures within seconds to minutes. New tools should be quantitative, have sufficient resolution to determine sub-micron sized defects and voids in TSVs at the wafer or package level. It should also measure thickness and their material composition of multilayer structures above the wafer surface, such as microbumps, or those below the surface including UBM and RDL. In this paper we are introducing a novel x-ray fluorescence microscope technique capable of solving the above applications in advanced packaging for PFA and process development. The same technique can also be applied in the front end metrology of new gate materials, 3D FinFET structures within test structures in patterned wafers. Characterization of sub nanoscopic changes (sensitivity of sub-angstrom) in film and dopants deposited in 3D structures will also be shown. With its high sensitivity for trace materials, contamination analysis of post hard mask residue, post metal etch residue especially in high aspect ratio structures is also possible.

Infrared optical probing techniques that have significant applications to and continued development for silicon physical debug have existed for decades. More recently, resolution enhancement achieved by improving numerical aperture, etc. have reached fundamental limits and the ability for resolution to match node scaling with radiation transparent to silicon (photon energy < silicon bandgap) becomes diffraction limited for some 10nm and many future process nodes. Decreasing the wavelength used for imaging and signal acquisition can improve resolution; however, it is well documented that absorption increases sharply for photons with energy greater than the bandgap of the bulk substrate material. Significant reduction in the thickness of the backside substrate material can be performed to achieve acceptable transmission through the absorbing substrate, but the requirement for very thin sample preparation significantly modifies the thermal system surrounding active circuitry. Here, high aspect ratio trenches are shown to offer a unique method to take advantage of thick silicon (> 100µm) for lateral heat dissipation as well as thin silicon (< 2µm) for minimally absorbing optical path in close proximity to enable case-by-case preparation methods for postsilicon labs faced with visible light resolution requirements on high power density circuits.

In 1986 the Atomic Force Microscope (AFM) was invented by Gerd Binnig, Christoph Gerber, and Calvin Quate [1]. Since then, numerous analytical techniques have been developed and implemented on the AFM platform, evolving into what is collectively called the Scanning Probe Microscope (SPM). The SPM has since become well established as a mainstream analytical instrument with a continually increasing role in the development of nanoscale semiconductor technologies providing critical data from initial concept to technology development to manufacturing to failure analysis [2]. Scanning Capacitance Microscopy (SCM) has a longstanding, well-established track record for detecting dopant-related mechanisms that adversely affect device performance on planar (Field Effect Transistor) FETs as well as other structures (e.g., diodes, capacitors, resistors). The semiconductor industry’s transition to three dimensional FinFET devices has resulted in many challenges with regard to device analysis. This is especially true when it is necessary to perform detailed dopant analysis on a specific device; the device may be comprised of a single or multiple fins that have been called out specifically through traditional fault localization techniques. Scanning Capacitance Spectroscopy (SCS) is an analytical method, implemented on the SCM platform in which a series of DC bias conditions is applied to the sample and the carrier response is recorded using SCM [3]. SCS has a proven history of highlighting dopant related anomalies in semiconductor devices, which, in some instances, might not otherwise be “visible”. This paper describes successful application of SCM and SCS in showing, in full detail, a dopant-related failure mechanism on an individual, location-specific 14 nm FinFET.

Using a laser to purposely damage (or zap) a static random-access memory (SRAM) bitcell for bitmap validation purposes is a well-established technique. However, the absence of visible damage in FinFET SRAM cells, amongst other things, makes precision zapping in these devices more difficult. In this paper, we describe system enhancements and a modified workflow for bitmap validation of these devices using precision, near-infrared (NIR) laser-induced damage. We also explore the use of laser perturbation and non-precision zapping options. Examples are provided.

The visible approach of optical Contactless Fault Isolation (VIS-CFI) serves the perspective of application in FinFET technologies of 10 nm nodes and smaller. A solid immersion lens (SIL) is mandatory to obtain a proper resolution. A VISCFI setup with SIL requires a global polishing process for sub-10 µm silicon thickness. This work is the first to combine all these necessary components for high resolution VIS-CFI in one successful experiment. We demonstrate Laser Voltage Imaging and Probing (LVI, LVP) on 16/14 nm technology devices and investigate a focus depth dependence of the LVI/LVP measurement in FinFETs.

Physical failure analysis of nanoelectronic devices is typically performed using plan view or cross-sectional TEM, SEM or SPM techniques. While plan view SPM and SEM analyses are limited by the depth sensitivity of the technique, cross-sectional analysis requires at least approximate localization of the fail location within the device for effective sample preparation. Multi-finger wide 2D planar devices and multi-FIN 3D devices are structures which require an additional step in pinpointing the fail area within the device. This paper describes successful use of EBIC/EBAC techniques to localize the fail location within such devices in both the 22 nm and 14 nm technology nodes.

The FinFET has been introduced in the last decade to provide better transistor performance as the device size shrinks. The performance of FinFET is highly sensitive to the size and shape of the fin, which needs to be optimized with tighter control. Manual measurement of nano-scale features on TEM images of FinFET is not only a time consuming and tedious task, but also prone to error owing to visual judgment. Here, an auto-metrology approach is presented to extract the measured values with higher precision and accuracy so that the uncertainty in the manual measurement can be minimized. Firstly, a FinFET TEM image is processed through an edge detecting algorithm to reveal the fin profile precisely. Finally, an algorithm is utilized to calculate out the required geometrical data relevant to the FinFET parameters and summarizes them to a table or plots a graph based on the purpose of data interpretation. This auto-metrology approach is expected to be adopted by academia and/or industry for proper data analysis and interpretation with higher precision and efficiency.

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

Dynamic Laser Stimulation using Continuous Wave (CW) Lasers has been a very important technique in fault isolating soft failures due to process defects and design speed paths in microprocessors. However, the rapid scaling down of the process technologies and the high density of logic laid out in silicon has made it difficult to precisely fault isolate using a conventional continuous wave laser which has a laser spot size of about ~300nm. Also, the remnant effects of a CW laser DLS like banding due to n-well interactions make it further difficult to achieve high resolution fault isolation. In this paper we discuss how by using a modulated pico-second pulsed laser, a DLS suspect is isolated to cell internal nets, which using a CW laser spanned across multiple cells. This is achieved by modulating the pulsed laser using an Electro-optical modulator and restricting the stimulation to only those parts of a test-pattern where the signal propagation occurs. Also, by synchronizing the pulsed laser with the clock of the test-program and changing the laser pulse delivery in time, high stimulation levels were achieved without being invasive. This revealed extra data points (DLS sites) that can help with making precisely accurate Physical FA plans that reduce turnaround time and also ensure high success rates. Specifically, in the case of a bridging defect between two nets wherein DLS sites were only seen on the victim net using conventional CW laser, the time resolved pulsed laser revealed DLS sites on the aggressor net as well. This confirmed the bridging between the two nets since the aggressor net was not electrically connected with the victim net. We discuss in detail how the DLS sites play their role in framing the perfect Physical FA plan. A detailed study of the resolution achieved using time resolved pulsed laser and its comparison with the same using a CW laser is shown on 14nm FinFET technology.

Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.

For a recent replacement metal gate (RMG) technology using a SOI substrate, residue from the dummy gate formed a defect that affected the RMG formation. In this FINFET technology, the high aspect ratio of the gate makes removing the dummy gate very difficult. Residue is left behind, especially in multi-fin structures. This residue was poorly detected by existing Broad-Band-Plasma inspection and thus required Electron Beam Inspection. However, this physical inspection is challenging due to high aspect ratio of the gate and an insulating wafer surface. The defect was verified using TEM, and careful sample prep is shown to be critical to verify the defect. The high aspect ratio and insulating sample in a charged-particle inspection is investigated with Monte-Carlo (MC) simulations.