Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Moore”). This complex 3D geometry, with an abundance of opaque layers and interconnects, presents a great challenge for failure analysis (FA). Three-dimensional (3D) magnetic field imaging (MFI) has proven to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allows for submicron vertical resolution. 3D X-ray microscopy (XRM) enables 3D tomographic imaging of advanced IC packages without the need to destroy the device. This is because it employs both geometric and optical image magnifications to achieve high spatial resolution. In this paper, we propose a fully nondestructive, 3D-capable workflow for FA comprising 3D MFI and 3D XRM. We present an application of this novel workflow to 3D defect localization in a complex 2.5D device combining high bandwidth memory (HBM) devices and an application specific integrated circuit (ASIC) unit on a Si interposer with a signal pin electrical short failure.

Anamnesis is known as an important method for pre-diagnosis in medical sciences. In device failure analysis (FA) it is not so far used, yet – especially with regard to system- and application-aspects. As a consequence, a lot of useless rootcause-related FA efforts are done on device level, while the root cause is on system level. Introduced by an illustrative case study, the benefit of a suitable anamnesis is shown as well as the way to do it – by posing the right questions before FA starts. Many FA efforts can be saved or optimized and frequently, a sound anamnesis already may lead towards the root-cause conclusion.

Multiple, independent, system level test failures that occurred around the same time were traced back to a short circuit on the same type of printed circuit board (PCB). The PCBs were removed from the application and sent to the authors' lab for analysis. This paper reviews the analysis techniques and results that led to the failure mechanism being identified. The discussion focuses on steps taken to exonerate the authors' lab and processes as possible sources of contamination. Additional investigation that leads to the conclusion that the issue is systemic is also covered. The paper then focuses on the containment effort as well as root cause identification at the manufacturers. It was concluded that the failure mechanism causing the short circuit in the failed PCB is due to ionic contamination trapped inside the PCB. The normal chemistry required to process the plated through holes contaminated the voids/fractures created by drilling process.

This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.

The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

This paper deals primarily with the difficulties and solutions to scanning transmission electron microscope (STEM) sample preparation by dual beam focused ion beam. Approximately twenty major challenges were encountered spanning hardware, software, and material sample preparation. The main focus is upon the variety of challenges which are encountered in trying to implement automated STEM and TEM sample fabrication with minimal operator input and the engineering solutions implemented to overcome these challenges. The automated STEM script has evolved significantly from the first generation attempt and is described in more detail in this paper. The mechanical, software, and materials challenges encountered are also presented. The paper highlights a mechanical issue with the ion aperture motor mechanism, which required extensive troubleshooting to fully diagnose and correct. A long standing software routine had to be modified to fully enable script automation by extending the beam dwell time of the automatic brightness contrast routine.

Electrical fault isolation constitutes the first steps in characterizing and isolating the failure modes and root causes of a failing motherboard. Ideally the Failure Analysis Test tools provide complete coverage of all motherboard buses and silicon devices. Time and resource constraints for tool development prevent complete coverage, however, so the challenge is to provide the highest level of debug test coverage in the shortest development schedule. A simplified Fault Isolation process has been created based on historical failure analysis data to reduce the development time and resources to create tools which allow diagnosing failure root causes on high-end server motherboards. This strategy prioritizes the most common types of electrical failure modes and the types of Electrical Failure Analysis / Fault Isolation (EFA-FI) tools best suited to diagnose these modes. The benefits of this strategy include shorter EFA-FI development times, equivalent success rates in failure root cause, lower costs, and more effective EFA-FI tools that can be used within the Design Team and at either OEM or Contract Manufacturing sites.

Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.

The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.

In the failure analysis (FA) of an organic light emitting diode (OLED) display device, fault isolation and physical failure analysis (PFA) were used to identify the root cause of display failure. It is challenging to conduct the FA of a display device, as it consists of display panel, a circuit board and components like semiconductor chips and this integration makes the failure complicated and difficult to analyze and understand. In the case of the display failure studied in this paper, the first work of fault isolation did not clearly identify the origin of the malfunction and its PFA didn’t show any specific defects. To precisely identify the defect location before destructive analysis, the fault isolation technique of OBIRCH was applied to the display device and subsequent PFA successfully identified a crack defect causing the display failure. This finding was given as feedback to the wafer fab and processing parameters were adjusted to prevent generation of the defect in the OLED display device.

This paper presents conceptual application of AI in Failure Analysis to connect to various databases in semiconductor manufacturing and generating interactive data visualization to isolate root cause of failure faster vs traditional methods. Generally available low-cost software application like Microsoft Power BI (Business Intelligence) is utilized to visualize big data to isolate failure modes at wafer, die, and package level. This historic data visualization knowledge is further used by failure analyst to process failure mode isolation much faster based on failed package unit history. Semiconductor manufacturing companies have various big data such as wafer fab processing, die level test, or wafer sort and packaged die testing including customer return. MS Power BI application has ability to connect to these separate big databases and create unified data visualization to isolate failure modes through faster inter-connectivity and "connecting the dots" to provide bigger picture or drill down to finer unit level detail. This level of visualization utilizes already available info/data to help reduce overall time-to-defect. With this failure background, engineers can plan fault isolation and analysis and reduce overall time to find root-cause of failure.

Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

With the increasing complexity of packaging technology, especially Flip-chip, package failure analysts face challenges to identify failure root cause. Due to the complex construction of Flip-chip packages, the conventional failure analysis process flow needs to be enhanced. Thus, generating a bench marked failure analysis process flow specifically for Flip-chip packaged devices becomes necessary. In this paper, the failure analysis process flow for Flip-chip package devices along with different failure mechanisms will be discussed and demonstrated. For instance, even in a simple continuity-open failure, instead of cross-sectioning the device as the initial fault identification step, the process flow details how to start from non-destructive C-SAM, TDR, to destructive die removal, polishing and finally cross-sectioning.

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

In this paper, three low yield case studies in wafer fabrication are reviewed. These issues/problems include thicker gate oxide due to contamination from the wafer fab process, QBD failures due to silicon crystalline defects caused by charging during the BN+ implant process and memory failures relating to tunnel oxide defects in EEPROM devices. Chemical deprocessing techniques, 155 Wright Etch, Scanning Electron Microscope, Transmission electron microscopy & Secondary Ion Mass Spectroscopy were used to identify the root causes. Some new chemical deprocessing techniques in exposing the tunnel window & oxide for the memory cell failures were developed. Moreover, some new failure mechanisms relating to the low yield due to thicker gate oxide, silicon crystalline defects and QBD failure were also discussed.

For its latest generation of high performance logic applications, Motorola employs a 0.13 µm CMOS technology with shallow trench isolation (STI). The contact dimension and spacing requirements for the dense areas of the circuitry, such as the cache, are quite aggressive. We recently encountered single bit and massive array failures, which were traced to an electrical short between tungsten contacts. We report here the failure analysis, which involved electrical and physical testing techniques.

Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

Device failure analysis typically requires multiple systems for fault identification, preparation and analysis. In this paper we discuss the practicalities and limits of using a single FIBSEM system for a complete failure analysis workflow. The theoretical requirements of using a nanomanipulator for both lamella lift out and electrical testing are discussed and the current capabilities of windowless X-rays detectors for chemical analysis demonstrated. When the required resolution for failure analysis exceed the limits of a FIBSEM and TEM is required, the combination of the nanomanipulator and X-ray detector for advanced lift out and thickness controlled thinning techniques are demonstrated to prepare exceptional quality lamellae.

In the failure analysis of semiconductors, layout analysis to pick up suspect nets is getting to be a time consuming work due to finer wiring pitch and multi-layer structure. This article proposes a failure analysis navigation system (FA-Navigation System), which can make it easier to extract the nets passing through the signals detected by the hardware analysis tool, such as emission microscopes or OBIRCH analysis tools. It introduces the functions of the system and shows some case studies in actual failure analyses. The IDDQ fault diagnosis is especially useful for case studies. The result of the software diagnosis can be loaded in the analysis window of the FA-navigation system, and the system correlates the result to the nets extracted by the hardware analysis and displays coincident nets in a sorted manner to make the failure analysis easier.