Abstract There are many wafer level tests, such as Fail Bit Count (FBC), where conventional statistical analysis methods are inadequate because the associated data do not follow a normal distribution. This paper introduces a statistical failure analysis technique that does not rely on location and scale parameters and is thus able to handle such cases. It describes the math on which the method is based and explains how to determine effect size (ES) using the quantile comparison equivalence criteria (QCEC) and a statistical parameter, called the center of dispersion (CoD), that distinguishes between center difference and dispersion difference. It also includes a case study showing how the new method is used to assess the effect of a process change on dynamic random access memory test data and how it compares in terms of accuracy with conventional statistical techniques.

Abstract ATPG diagnosis is an essential part in failure analysis and is proven to be an effective technique in isolating faults in the digital core. In many single failure cases however, ATPG diagnosis could yield either incorrect candidates or includes a large amount of equivalency which limits diagnostic resolution. While iterative ATPG diagnosis improves diagnostic resolution, there are many cases where the resolution is still insufficient. This paper will discuss a methodology that helps the analyst understand and complement ATPG diagnosis by using an approach called “single shot logic patterns”. New patterns that each target one singular fault in the area of interest provide the failure analyst with simplified analytical data. This process is repeated for each suspect candidate. The number of times a target fault is detected is increased for better resolution. Aggregating this analytical data with the layout and fan out of the net instances could provide greater resolution into the likely defective area. Furthermore, adding constraints can also be used to further simplify the test and/or control the fan out of failures. Only equivalencies where there is observable fan out can achieve greater diagnostic resolution. ATPG tools have been observed to not always maximize this fan out.

Abstract Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.

Abstract Electrical fault isolation constitutes the first steps in characterizing and isolating the failure modes and root causes of a failing motherboard. Ideally the Failure Analysis Test tools provide complete coverage of all motherboard buses and silicon devices. Time and resource constraints for tool development prevent complete coverage, however, so the challenge is to provide the highest level of debug test coverage in the shortest development schedule. A simplified Fault Isolation process has been created based on historical failure analysis data to reduce the development time and resources to create tools which allow diagnosing failure root causes on high-end server motherboards. This strategy prioritizes the most common types of electrical failure modes and the types of Electrical Failure Analysis / Fault Isolation (EFA-FI) tools best suited to diagnose these modes. The benefits of this strategy include shorter EFA-FI development times, equivalent success rates in failure root cause, lower costs, and more effective EFA-FI tools that can be used within the Design Team and at either OEM or Contract Manufacturing sites.

Abstract The analyzed new Application Specific Integrated Circuit (ASIC) design failed latch-up test on two input pins during current stress. In order to determine the root cause, the Failure Analysis (FA) with use of backside Emission Microscopy (EMMI) was performed. The EMMI results were followed by detailed layout and circuit analysis. It was found that the root cause of the latch-up is an abutment of two specific cells (called “cell C” and “cell D”), where the N-well was grounded creating a parasitic NPN transistor sustaining the latch-up. A detailed calculation of parasitic interconnection resistances from the layout revealed some differences between latching and non-latching pins. The analytical model to explain the latch-up behavior based on parasitic resistances was applied successfully to root cause analysis. Summarizing, the latch–up behavior can be explained by the abutment of cells C and D, parasitic interconnect resistances and cell location with respect to the substrate bumps. In conclusions the following recommendations were made: 1. Remove the n-well in cell D; 2. Connect specific cells (B and D) to higher supply voltage; 3. Implement p+ guard rings for cells C and D; 4. Optimize placement of ground bumps; 5. Eliminate abutment of cell C and D.

Abstract A new logic-model derivation method for leak faults observed by light-emission microscopy (LEM) or in liquid-crystal analysis (LCA) has been developed to verify those faults by comparing them with failures observed on an LSI tester. Since CMOS devices display various kinds of faulty behavior depending on leak resistance, it is essential to include the effects of this resistance in logic models. Considering that the resistance of leaks observed in LEM and LCA ranges from 10 to 10,000 ohm, the new logic models have been derived so that the leak fault could be easily incorporated into logic simulators without SPICE simulation. The feasibility of the proposed method has been demonstrated by using it to diagnose LEM and LCA faults causing logic failure in a 20k-gate logic LSI circuit.

Abstract With the ever decreasing trend in accessibility to hardware tools, the need for software tools is becoming greater than ever for IC fault diagnosis. In this paper, we present a process of studying the limitations and capabilities of fault diagnosis using automated Diagnosis tools, such as FastScan™, as applied to a programmable, parallel processing DSP, The Multimedia Video Processor (TMS320C80). Starting with a brief description of the MVP, we describe how FastScan™ is integrated for supporting fault diagnosis. For establishing the effectiveness of FactScan™ as a diagnostic tool, both the simulation and manufacturing modes of evaluation were done. In simulation mode, both the fault model and the heuristics used by the fault diagnosis software are tested by inserting known defects using a focused ion beam (FIB), machine. This process is then repeated with unknown defects in unknown locations. Experiments on several chips demonstrate the value of the tool and its limitations in relation to detection of classic stuck-at faults and some realistic faults, such as bridging defects.

Abstract Logic fault diagnosis or fault isolation is the process of analyzing failing random logic portions of a chip to isolate the cause of failure. Fault diagnosis or fault isolation (FI) plays an important role in multiple applications at different stages of design and manufacturing. Most currently deployed FI techniques for random logic fault isolation include physical techniques with limited automated diagnosis followed by e-beam and/or laser voltage probing (LVP) on packaged parts. This paper will present the methodology and FI results obtained by executing automated scan based diagnosis on a chipset product (440BX). The logic diagnosis techniques used are presented along with simulation and Failure Analysis (FA) results

Abstract We present for the first time the results of a comprehensive study of the increase in propagation delay of multi-GHz digital signals due to backside FIB fabricated interconnects. Signal propagation delays were measured in 90nm CMOS technology circuits as a function of interconnect material properties and physical dimensions. We compare the empirical results of this study to SPICE calculations, which were based on an equivalent circuit element model of the interconnect. We show that the empirical data obtained in these experiments supports the validity of the equivalent electrical model for the frequency range typically encountered in modern microprocessor debug. Based on the results or our analysis, we comment on the future capability of backside FIB circuit edit (CE) interconnection technology as it pertains to the debug of flip-chip packaged IC’s operating at multi-GHz frequency.

Abstract Reduced noise immunity due to dimensional shrinkage, lower operational voltages and increasing densities results in increased soft or random failures. In practice, noises are generated by complex operation of device. In Dynamic Random Access Memory (DRAM), failures by noise are regarded as either decrease in charge at cell capacitor or increase in systematic interferences. Simple equivalent circuit of One Transistor One Capacitor (1T1C) DRAM and theoretical approach in time-domain are provided for quantitative noise analysis related to sense amplifier circuitries. Results show that local voltage fluctuation reduces sensing margin to judge data-0 or data-1. This phenomenon is easily observed at 1T1C with high resistance because response of voltage generator is comparatively slow.

Abstract In this paper, DACS stands for Defects that Affect Chain and System, which could be any type of silicon defects caused by an unintentional interaction between a scan chain signal and a system logic signal. The device could fail scan chain testing or show up as a latent failure in the customer’s system. A novel diagnosis methodology is proposed to locate both ends of a DACS. The proposed algorithm can be generally applied to any type of DACS. Experimental results on industrial chips demonstrate the effectiveness of the proposed method.

Abstract Scanning transmission electron microscopy with scanning electron microscopes (SEM-STEM) has become increasing used in both SEM and dual-beam focused ion beam (FIB)-SEM systems. This paper describes modeling undertaken to simulate the contrast seen in such images. Such modeling provides the ability to help understand and optimize imaging conditions and also support improved sample preparation techniques.

Abstract Looping on test vectors is a widespread requirement in failure analysis of semiconductor devices. The start of the loop and the number of vectors in the loop can be of critical importance. Present-day vector memory architecture tends to impose restrictions on both due to test speed requirements. A new Vector Loop Transformation algorithm is introduced to remedy the tester constraints.

Abstract As the TSV count increases, chip yield can be severely degraded due to failures during the TSV or die-stacking processes. This paper will present and discuss on the usage of failure masks designed to detect and differentiate failure types such as connection failure and insulator failure based on frequency-domain one point probing measurement. The failure masks are proposed on the basis of the frequency domain analysis of TSV failures with Z11 magnitudes.

Abstract Focused Ion Beam is commonly used for IC repairs and modifications. However, FIB operation may also induce a damaging impact which can takes place far from the working area due to the charge-up phenomenon. A complete characterization joined to an in-depth understanding of the physical phenomena arising from FIB irradiation is therefore necessary to take into account spurious FIB induced effects and to enhance the success of FIB modifications. In this paper, we present the effects of FIB irradiation on the electrical DC performances of different electronic devices such as nMOS and pMOS transistors, CMOS inverters, PN junctions and bipolar transistors. From the observed behavior of the DC characteristics evolution of the devices, some suggestions about physical mechanisms inducing the electrical degradation are proposed.

Abstract Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses IDDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of IDDQ contour plots. A “family” of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.

Abstract We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

Abstract A novel laser based technique for waveform probing of integrated circuits is presented. This new technique exploits polarization-dependent opto-electronic effects in silicon integrated circuits to give phase sensitivity via a simple common-path interferometer design. The system utilizes a 10 ps pulse-width mode-locked laser to generate equivalent-time sampling pulses. A custom wavelength-tunable and spectrally matched external-cavity laser diode source is used for noise cancellation. A 20-GHz intrinsic system bandwidth with a 2x lower noise-floor, in comparison to current laser voltage probing technology, is shown.

Abstract Logic diagnosis is the process of isolating the source of observed errors in a defective circuit, so that a physical failure analysis can be performed to determine the root cause of such errors. In this paper, we propose a new “Effect-Cause” based intra-cell diagnosis approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing (CPT) here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.

Abstract It is shown in this study that it is possible to modify under a controlled way the resistance of a passive component either through the milling of part of the volume of a polysilicon resistor or on the contrary through the deposition of a Pt strap parallely connected to the involved device polysilicon resistor. In the latter case, each modification step being followed by an electrical characterization, the evolution of device VCO phase noise versus equivalent resistor value could be drawn and the optimum value quantified.