Microelectromechanical systems (MEMS) that sense, think, and act are enabling technologies currently employed in many industrial applications. To operate these devices, a stimulus is required to produce motion. In MEMS, this stimulus may be thermal actuation using current to produce joule heating, or electrostatic actuation using voltages to create electric fields. To qualify MEMS technology, these devices must undergo repeated characterization and testing and at both the die and system level. Electrical overstress (EOS) and electrostatic discharge (ESD) are two important tests used to assess the robustness of a device to steady state and sharp voltage and current transients. Identifying the failure mechanism and understanding the root causes for failure is paramount to the overall improvement and success of any MEMS based system. In this paper we will focus on the effects of EOS and ESD events on surface micromachined polysilicon based electrothermal actuators fabricated using the SUMMiT V™ process.

In this paper, an IC failure case by EOS is presented. The optical microscopy, SAM, and X-ray were used for the non-destructive analysis. The decapsulation, SEM, FIB were used for the destructive analysis. It was found that IC’s presented in this case were electrically overstressed (EOS), which caused the uncontrollable overheating. The EOS symptoms can be various, such as electromigration, intermetallic compound formation, delamination on die surface, circuit track damages, and wire bonding broken. The latch-up testing and deprocess technique were used to simulate the failures and it was found that the failures in this case was due to latch-up. The results show that failure symptoms of EOS are various and their identifications require different failure analysis techniques and tools.

Frequently, Electrical Overstress (EOS) is understood in a similar context like Electrostatic Discharge (ESD). However, when looking deeper, only 3-5% of EOS failure signatures are caused by ESD. The dominant root causes can be found on system level – often inaccessible for the device failure analyst. However, switching procedures and sometimes-hidden inductance loads are the unconsidered and undiscovered problem makers. This paper reviews and highlights these failure mechanisms.

Electrical overstress (EOS) is a common failure cause for many of the electronic circuits today. The Failure Analyst has no difficulty identifying EOS as the cause of the failure. The difficulty comes from determining the source of the EOS event so it can be eliminated. This paper describes two case studies looking a gross EOS damage and very mild EOS damage. Close cooperation between the customer and vendor was required to determine the source of the EOS events.

The task of differentiating precisely between EOS and ESD failures continues to be a challenging one for Failure Analysis Engineers. Electrical OverStress (EOS) failures on the die surface (burnt/fused metallization) of an IC can be characterized mainly by the discoloration at the site of the failures. This is in direct contrast to the lack of discoloration characteristic of ESD failures, which occur almost exclusively below the die surface (oxide and junction failures). To aid in this distinction, this paper attempts to present the underlying physics behind the discoloration produced in the EOS failures. For the EOS failures, the metal fuses due to the longer pulse widths (sec to msec), while for the ESD failures, the silicon melts because of the shorter pulse widths (< < 500 nsec) and higher energy. After EOS, the aluminum surface becomes dark and rough and the oxide in the surrounding area becomes deformed and distorted, resulting in the discoloration observed in the light microscope. This EOS discoloration could be due to one or more of the following: 1) morphological and structural changes at the metal/glass interface and the glass itself; 2) changes in the thickness and scattering behavior of the glass and metal in the failed areas.

The response of aluminum interconnect to electrical overstress (EOS) is an important component of semiconductor reliability. Proper modeling of the fusing characteristics are necessary to build more robust circuits without wasting die area and allow estimation of the events that cause failures. This paper reviews previous work on aluminum EOS and presents experimental evidence of the mechanisms involved in aluminum EOS. From this evidence a simplified model is proposed based on the physical characteristics of the structure.

Some of the most challenging task in analyzing fractures is a die that has not been fully cracked apart and a cracked die with electrical overstress damage. Traditional tools such as simple magnifying lens, optical microscope and up to the advance Scanning Electron Microscope are not enough to study the internal fractures or markings that could lead back to the origin of the crack. In order to study these internal fractures, the analyst tends to break the sample into pieces. However, this method creates additional mechanical stress and leads to a secondary crack where the point of origin will be difficult to analyze. This paper aims to introduce infrared microscopy in fractography (mainly on silicon) using cases and techniques to minimize the occurrence of secondary crack in analyzing internal fractures.

Failure analysis at the system level requires a well-defined process and methodology in order to drive quality improvements onto motherboards or other subsystems of a personal computer. This process needs to be structured around the type of failure mechanisms that an FA group desires to understand. This paper discusses a specific case study involving electrical overstress in a personal computer that impacted the motherboard of the system. The case study resulted in a solution to increase quality on motherboards in the context of electrical overstress prevention.

In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

During moisture-and-bias reliability stress tests of THBT (temperature and humidity biased test) and HAST (highly accelerated stress test) extensive electrochemical oxidation of a TiN ARC layer is seen to occur. This oxidation proceeds at the nominal temperatures and humidity levels associated with such THBT and HAST tests; excessive heating due to EOS (electrical overstress) or other anomalous electrical conditions was not involved. The oxidation rate increases with applied voltage. Metal line width also affects the spread of oxidation. Oxidation requires the presence of adequate humidity to act as an electrolyte, and therefore is seen to propagate wherever moisture penetration can occur in the passivation dielectrics. The presence of a silicone gel die coating is found to render the die more susceptible to TiN oxidation. Electrical failures – typically open circuits or increased resistance due to corrosion – are found to occur as a consequence of this oxidation and its effect on the surrounding structures. This mechanism is a concern for integrated circuits with TiN in the upper metal layers, operating at voltages >5V in humid conditions. Two approaches at reducing this electrochemical reaction are offered.

Finding the real root cause of electrically damaged devices is often challenging where it can mask out the real failure mechanism. The electrical damages might (might probably, one doubtful word is enough) be a consequence of the real failure mechanism. This paper aims to present cases and techniques to overcome the challenges of electrically damaged devices in identifying the real failure mechanism.

The fabrication of semiconductor devices is handling, processing and test verification intensive all of which present opportunities for electrical over stress (EOS) or electro static discharge (ESD) to occur. Well-documented models for ESD exist. These include Human Body Model (HBM), Machine Model (MM) and Charged Body Model (CBM), but such is not the case for EOS and its manifestations. In addition, as device technologies change and reduce in dimension these geometric reductions create increases in operating currents and magnetic fields located on the die surface. When there are occasions where devices are overstressed electrically in new device technologies, the manifestation or evidence of the EOS maintains the same appearance while physical dimensions have become much reduced. On occasions, the manifestation or evidence of EOS in some new device technologies tends to appear different from anything we have seen in past device technologies. The resolution of these new failure modes is not trivial to analyze. This case study will detail the diagnostic journey used to resolve one such new and unique failure, the “Star Crack”.

In today's electronic industry of shrinking circuit boards and shrinking semiconductor integrated circuits (IC), semiconductor companies have to be creative in providing devices with more circuitry on less silicon. Copper Bond over Active Circuit (BOAC)/Copper over Anything (COA) processes allow routing and bonding to thick top level metallization on the LinBiCMOS technology node. This paper discusses failure analysis (FA) techniques and approaches on un-passivated BOAC, and explains a generic BOAC/COA process. The approach to FA of BOAC involves package inspection-non intrusive analysis, decapsulation, die inspection, and defect identification/root cause analysis. Case studies are presented to explain the specific FA steps. Fault isolation involving BOAC requires the strategic removal of copper traces and selective analysis of the failed circuitry. Liquid crystal and micro-probing have been used effectively in failure isolation.

Metallurgically bonded, glass-bodied DO-35 power rectifier diodes were electrically overstressed by applying forward and reverse current pulses. Forward current pulses varied from 0.1 to 3 ms with current amplitudes varying from 200 to 1000 A were applied to one group of diodes. Reverse bias current pulses in the microsecond range with amplitudes from 2 to 400 mA (above breakdown voltage) were applied to another group. A small-step cross sectioning in combination with electrical probing, light emission microscopy, liquid crystal technique, and chemical staining were used to reveal and compare damage in three groups of diodes: two overstressed groups and the third group which had failed during burn-in electrical testing. Failure mechanisms and peculiarities of damage created in these diodes and several case histories related to different types of diodes are discussed.

A component failure has the potential to significantly impact the cost, manufacturing schedule, and/or the perceived reliability of a system, especially if the root cause of the failure is not known. A failure analysis is often key to mitigating the effects of a componentlevel failure to a customer or a system; minimizing schedule slips, minimizing related accrued costs to the customer, and allowing for the completion of the system with confidence that the reliability of the product had not been compromised. This case study will show how a detailed and systemic failure analysis was able to determine the exact cause of failure of a multiplexer in a high-reliability system, which allowed the manufacturer to confidently proceed with production knowing that the failure was not a systemic issue, but rather that it was a random “one time” event.

The need for high bandwidth, high speed interconnects with optimum routing through computer backplanes has led to the use of optical interconnects in multiprocessor computing systems [1]. Most of the current commercially available optical interfaces are based upon 850nm vertical-cavity surface-emitting lasers (VCSELs). Extensive studies conducted by the VCSEL manufacturers show that the reliability of these devices continues to improve [2-4]. In order to understand the risks and implications of using VCSELbased modules in computer systems, we have conducted an experiment designed to provide insight into the emission degradation and failure of VCSEL devices. In this paper we briefly describe the experiment and review the results of the subsequent failure analysis on degraded VCSEL arrays.

Transmission electron microscopy (TEM) coupled with scanning electron microscopy (SEM) were used to observe the damage caused by machine model (MM) electrostatic discharge (ESD) testing on the ESD protection circuitry of input pins stressed with different ESD voltages. Contact damage was observed in the n-well resistor of the ESD protection circuitry. TEM results of various cross-sections show the formation of a silicon melt beneath the contacts of the n-well resistor. Junction spiking was also observed on some of the stressed devices.

AOC herein describes a collection of material degradation features observed in Vertical Cavity Surface Emitting Lasers (VCSELs) that have been intentionally degraded with a range of electrostatic discharge (ESD) stress conditions. Failure analysis techniques employed include emission microscopy, Focused Ion Beam (FIB) microscopy and Transmission Electron Microscopy (TEM). The results have enabled higher confidence in root-cause determination for failed VCSEL devices.

For certain programmable logic type devices, the electrical, morphological and failure location differences in the ESD signatures between ICC failures and I/O leakage failures have been identified. Based on these electrical, morphological and physical failure signature locations, this case study confirms that distinctions can be made between the signatures associated with the likely stress modes for pin combinations like I/O-to-Vss, I/O-to-Vcc, I/O-to-I/O, Vssto- Vcc and Vcc-to-Vss. This separation also facilitated the correct identification of core failures which are mostly due to the supply-to-supply pin combination stress, but in some cases are due to the pin-to-supply tests.

For certain programmable logic type devices, the electrical, morphological and failure location differences in the ESD signatures between ICC failures and I/O leakage failures have been identified. Based on these electrical, morphological and physical failure signature locations, this case study confirms that distinctions can be made between the signatures associated with the likely stress modes for pin combinations like I/O-to-Vss, I/O-to-Vcc, I/O-to-I/O, Vss-to-Vcc and Vcc-to-Vss. This separation also facilitated the correct identification of core failures which are mostly due to the supply-to-supply pin combination stress, but in some cases are due to the pin-to-supply tests.