Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.

Direct measurements of circuit node signals without changing the performance of the circuitry are essential in modern FA but often impossible for recent IC technologies. This paper shows new methods, based on FIB backside circuit edit, allowing access to every existing circuit node at the device level, and discusses options for probing and discrete characterization.

Presentation slides for the ISTFA 2024 Tutorial session “Defect Localization Methods for Device Characterization and Yield Management.”

Certain device failures are especially difficult to analyze since they can only be reproduced under high speed and high power conditions, while also requiring the removal of standard heat dissipating packaging to get visual access to the chip. In addition to the challenge of heat generation density of devices increasing year by year, small hot spots in actual usage generate heat far in excess of the average, and heat dissipation performance needs to be more efficient and highly uniform. In addition, it is desirable to implement a cooling system that does not overly restrict the number and types of lenses that can be used, such as high and low magnification air gap lenses as well as a solid-immersion lens, which has been one of the challenges of existing systems. This paper reports on the development of a cooling system to address these challenges and to enable failure analysis on a device running at 200 W.

In this work we have investigated the results obtained using fault isolation techniques such as EMMI, OBIRCH and OBIC on a Wide band gap power device and in particular a 4H-SiC. We used YLF laser and Green Laser and showed the differences in the resulting hot spots. In the selected point, FIB cross sectioning and EDS analysis was performed. Once that the defect was shown, the differences the fault isolation results were discussed.

Near Infra-Red (NIR) techniques such as Laser Voltage Probing/Imaging (LVP/I), Dynamic Laser Stimulation (DLS), and Photon Emission Microscopy (PEM) are indispensable for Electrical Fault Isolation/Electrical Failure Analysis (EFI/EFA) of silicon Integrated Circuit (IC) devices. However, upcoming IC architectures based on Buried Power Rails (BPR) with Backside Power Delivery (BPD) networks will greatly reduce the usefulness of these techniques due to the presence of NIR-opaque layers that block access to the transistor active layer. Alternative techniques capable of penetrating these opaque layers are therefore of great interest. Recent developments in intense, focused X-ray microbeams for micro X-Ray Fluorescence (μXRF) microscopy open the possibility to using X-rays for targeted and intentional device alteration. In this paper, we will present results from our preliminary investigations into X-ray Device Alteration (XDA) of flip-chip packaged FinFET devices and discuss some implications of our findings for EFI/EFA.

In prior work, it was demonstrated that information about device turn-on can be obtained in a nanoprobing setup which involves no applied bias across the channel. This was performed on nFET logic devices in 7 nm technology and attributed to the Seebeck effect, or heating from the SEM beam. In this work, the experiments are continued to both nFET and pFET devices and on both 22 nm and 5 nm devices. Further discussion about the opportunities and evidence for Seebeck effect in nanoprobing are discussed.

As advanced device technologies scale to 5nm with dimensions getting smaller and materials change, it is difficult to control the sample preparation delayering end pointing by polishing. Therefore, it requires an alternative solution such as Xe+ PFIB (Plasma Focused Ion beam) Microscopy for accurate delayering control. PFIB can be used for planar Failure Analysis (FA) delayering but also for nanoprobing sample preparation. This paper introduces the detail of nanoprobing sample preparation by PFIB and discusses nanoprobing results on 5nm FinFET technology.

The results of analyses on a commercially available 7 nm SRAM, using an in-situ AFM inside a SEM, are presented. In addition to typical results for conductive AFM, a novel method is described that uses the SEM beam to prepare a region for additional material removal, thus bringing out clearer electrical data. This would be of exceptional value for technology nodes using cobalt as a contact material. Finally, techniques making use of the current from the SEM beam as the source of current during the measurement are described. The technique may have value for well resistance measurements using in-situ structures on live product, a survey of junction health, or the localization of point defects.

Device shrinkage and mitigation of off-state power consumption are crucial factors in dynamic random access memory (DRAM) product development. Given the market demand for high-quality devices, the reduction and fluctuation of DRAM cell retention time, caused by interface traps, required a suitable solution for improved product quality. In this study, we propose a device structure for the reduction of GIDL current by implementing a second gate oxide in the overlapping region of the gate and the drain, and to calculate an increment in the margin for other processes from the retention time improvements, the virtual a capacitance of the bit line/a capacitance of the storage cap(Cb/Cs) evaluation was performed. This study is expected to provide a solution to the trap-induced retention- time deterioration and assist in the development of next-generation DRAM.

The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.

This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

Advanced memory technologies are in demand with phase change memory (PCM) devices as a forefront candidate. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens is critical. In this work, TEM specimens from a GeTe-based PCM device at a partial SET state were prepared using a Xe plasma focused ion beam (pFIB) and polished to electron transparency using Ar ion beam milling. We will highlight the differences between Ga focused ion beam (FIB) and Xe pFIB TEM specimen preparation, the benefits of post-pFIB Ar ion beam milling, and show TEM results of the effects of partial SET programming of the GeTe PCM device.

For device qualification in harsh environments (space, avionic and nuclear), radiation testing identifies the sensitivity of the devices and technologies and allows to predict their degradation in these environments. In this paper, the analysis of the electrical characteristics and of the failure of a commercial SiC MOSFET after a Single Event Burnout (SEB) induced by proton irradiation are presented. The goal is to highlight the SEB degradation mechanism at the device and die levels. For failed devices, the current as a function of the drain-source bias (VDS) in off-state (VGS=0V) confirms the gate rupture. For the die analysis, Scanning Electron Microscopy (SEM) investigations with energy-dispersive X-ray spectroscopy (EDX) analysis reveals the trace of the micro-explosion related to the catastrophic SEB inside the SiC die. With a fire examination, similar to a blast, the SEM analysis discloses damages due to the large local increase of the temperature during the SEB thermal runaway, leading to the thermal decomposition of a part of the SiC MOSFET and the combustion with gaseous emissions in the device structure.

In failure analysis, demounting and mounting is one of the steps in preparation for the electrical verification of the device. Performing decapsulation while the unit is mounted on the printed circuit board (PCB) is one of the solutions to limit the repeated demounting, mounting, and re-balling processes. However, it can cause inadvertent damage to the device and the PCB when the acids overflow, which could hinder further electrical verification of the unit. In this study, a new method of decapsulation using aluminum tape is used to protect the device and PCB during the decapsulation process. Results show that the use of aluminum tape is an effective method for decapsulating packaged units on PCB. It can prevent damages such as external lead detachment after demounting, ball pad oxidation, and recovery of device failure due to heat application.

The ability to precisely remove the internal structures of a semiconductor device, layer-by-layer, is a necessity for semiconductor research and failure analysis investigation. Currently, numerous techniques are used, such as mechanical polishing, chemical etching, and gas assisted plasma focused ion beam (FIB) milling. However, all of these techniques have limitations in that they are unable to: (1) delayer a millimeter-scale area with nanometer-scale uniformity, (2) rapidly remove thick (>300 nm) device layers, or (3) perform automatic and accurate end pointing, which is challenging on thin (≤300 nm) device layers.

Presentation slides for the ISTFA 2023 Tutorial session “What Packages Are in Your Mobile Device?.”

Non-volatile memory is the most important memory device in IC chips. As a memory, embedded non-volatile memory (NVM) is a fundamental structure in many kinds of semiconductor devices. It is commonly used in the modern electrical appliance as a code or data memory. For different applications, there are different memory designs or IP, like ROM, OTP, Flash, MRAM, PCRAM etc. The physical mechanism of these NVMs are different, some are electron based, some are resistance based and fuse or anti-fused based. The experiment described in this paper is performed on an electron charge storage based NVM. That means a medium is employed to store electron charge to differentiate two statuses “0” and “1”. Floating Poly gate is this medium used as electron charge storage in this NVM. Since the storage medium is in floating condition, it cannot be accessed externally. The methods of performing direct analysis are limited for this kind of device, especially in the case of subtle defects or soft fail. As semiconductor devices scale, the defects become smaller and more subtle. Nanoprobing is usually the only way to find the defect location electrically before any further physical analysis. In this experiment, the single bit NVM fail was analyzed. Different PFA methods used during the analysis, failed to find the defect. Nanoprobing was employed to precisely isolate the defect. Key word: nanoprobing, NVM, subtle defect, Poly-crystalline, floating gate

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

Stress induced pinholes, cracks, and 'craters' have been found in the gate oxide of a double level metal, single level poly CMOS device containing both analog and digital circuits. These defects have been found randomly across the die in active gate regions, and were found in a line parallel to the gate width. These defects were hidden beneath the polysilicon, and were virtually undetectable electrically. The only electrical indication was a slight shift in the threshold voltage, still within specification limits. The polysilicon had a compressive layer of tungsten silicide (WSi x ) as a cap to lower the polysilicon resistivity and increase circuit speed. It was believed that polysilicon grains or WSi x spikes were migrating into the gate oxide during the WSi x annealing process. The defects were found in unstressed, untested parts, and in parts that passed all tests and stresses. Backside silicon removal showed defects in the gate oxide layer, and subsequent FIB sectioning revealed a WSi x spike. Several techniques were employed to verify the gate oxide defects. Electrical and destructive physical analysis techniques will be presented in the paper.