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design validation

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Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 546-551, November 14–18, 2004,
... test failure analysis focused ion beam Iddq leakage current integrated circuit modification sample preparation semiconductor devices silicon wafer level test On Wafer Design Validation through Complementary Dual-Side Circuit Editing using FIB Mark A. Thompsona, Calvin Chena, Ming Hanb, Hun...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 443-448, October 28–November 1, 2018,
... on-silicon experiments on an advanced Fully-Depleted Silicon-On-Insulator (FD-SOI) technology node. advanced fully-depleted silicon-on-insulator technology design for manufacturability guidelines design of experiments integrated circuits pattern matching rule ranking silicon validation Pattern...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 202-208, November 15–19, 2020,
... verification IC Decomposition and Imaging Metrics to Optimize Design File Recovery for Verification and Validation Adam R. Waite, Jonathan H. Scholl, Joshua Baur, Adam Kimura Battelle Memorial Institute, Columbus, Ohio, USA waite@battelle.org Michael Strizich MicroNet Solutions, Inc., Albuquerque, New...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 337-341, October 31–November 4, 2021,
...Abstract Abstract With manufacturers now capable of creating transistors in the 5-7 nm node range, the ability to isolate, inspect, and probe individual metal and via layers is of the utmost importance for defect inspection and design validation. These isolated layers can be inspected...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 68-75, November 6–10, 2016,
...Abstract Abstract Laser scanning microscope (LSM) based waveform acquisition is widely used in advanced CMOS IC design validation and debug application. Complex waveforms obtained from LSM probing on CMOS ICs are often difficult to fully comprehend without deep understanding of the complex...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 122-128, November 15–19, 2020,
... in a design validation exercise in which we were asked to modify the drive of a multi-finger FinFET device structure to reduce its switching speed impact on a circuit. The original sized device pulled the next node in the chain too fast, resulting in a timing upset. Deleting whole structures and bridging over...
Proceedings Papers

ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 111-117, November 3–7, 2013,
...Abstract Abstract Focused ion beam (FIB) tools for backside circuit edit play a major role in the validation of integrated circuit (IC) design modifications. Process scaling is one of many significant challenges, because it reduces the accessible area to modify transistors and IC interconnects...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 54-59, November 13–17, 2011,
...-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 306-311, November 4–8, 2007,
... and affordable setup. This article provides information on design planning, application, validation, and deployment of WAFT as well as on transmit quality and receive quality evaluation. WAFT has been validated in providing accurate measurement by benchmarking with the existing tools. WAFT provides...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 345-351, November 15–19, 2020,
.... The proposed methodology is validated on silicon data for one modern large SOC design and successfully identified all scan cells with hold-time issues, which were validated by STA with corrected models. The subsequent mask fixes for these identified hold-time violations resolved this yield issue...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 366-371, November 10–14, 2019,
... of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 398-402, November 5–9, 2017,
.... The validation of such relative to its original form and competitor products is discussed where we demonstrate a doubling in performance and an approximate 50% increase in current handling capability. This type of analysis and application specific approach to innovation enables one to focus design improvements...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 204-208, November 10–14, 2019,
... for rapid prototyping of potential semiconductor design changes without the need to run a full manufacturing cycle in a semiconductor Fab. By FIB editing a completed module, thorough testing on the bench or in a full system can be achieved. Logic can be toggled, validation of speed enhancements performed...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 157-171, November 15–19, 2020,
.... Afterward, this assures that the most correct via is detected if two tiers detected vias at the same center location but different radii size. Before translating these pixel-level results into physically manufacturable designs, the final step is taken by the reverse engineer operator to validate and remove...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 76-81, November 1–5, 2015,
... designers to validate and analyze the EMC/ESD capability of electronic systems without TLP pulsers, ESD simulators, or precision inductive current probes. electromagnetic compatibility electronic systems electrostatic discharge failure analysis near field scanning equipment Near field EMC...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 477-483, November 14–18, 1999,
... major purposes during a product’s ramp. The first is to perform in-situ verification of logic and timing related design changes, and the second is to provide engineering samples to enable further debug for system and tester level validation. In both cases, sample generation using silicon microsurgery...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 1-8, November 10–14, 2019,
... in the presence of multiple hot spots was also demonstrated. For axial localization, the phase shift values have been extracted as a function of frequency [4]. For comparative validation, LIT analyses were conducted in both square wave and arbitrary waveform excitation using custom designed and sample-specific...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 277-282, November 10–14, 2019,
...Abstract Abstract The development of a characterization workflow for reliable pore characterization of porous metals especially for microelectronics applications is very important. This will help to provide design guidelines for the production and for the improved reliability of the devices...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 130-133, November 4–8, 2007,
... in Vcc pin (ISBLO), and high standby current in Vccq pin (ISBLOQ). Backside chip-outs are observed on Die 1 and Die 3 of the three failures. Electrical validation showed that only Die 3 is failing. Corner crack on Die 3 is common to the blown_up and ISBLO failing units while crack on Die 3 backside...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 396-401, November 2–6, 2008,
... on the tester. The approach includes validation of the hold-time fault model, characterization of the failure behavior in terms of Vdd and data dependencies and finally localization to a cone of logic including the data paths and the clock trees. This method of hold-time localization is organized into three...