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design for test

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Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 276-278, November 12–16, 2006,
... interactions reliability performance semiconductor chips Rapid Yield Learning with Effective Integration of FMEA design for DOE on Test Chip Ivan A. N. Goh, Russell McMullan, Brock Fairchild, John Ilzhoefer Foundry Technology Engineering, Texas Instruments Inc., 13560 North Central Expressway, MS3735...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 283-290, November 14–18, 2004,
...Abstract Abstract The fact that most components on prototype motherboards are likely to be from the same, or nearly the same manufacturing lot, and hence do not show the same variation that may be seen between lots during mass production, magnifies the deficiencies in the design and test...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 395-400, November 6–10, 2005,
... Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs Christian Burmer, Andreas LemMger, Hans-Peter Erb, Markus Gruetzner, Thomas Schwemboeck, Stefan Trost Infineon Technologies, Failure Analysis, Munich, Germany Christian. Burmer@in fineon, corn Abstract During yield ramp, quick...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 703-712, November 3–7, 2002,
... Design and Test Laborator y Electr ical and Computer Engineering, Por tland State University Portland, OR 97207 Abstract The subject of this paper is statistical post-processing of wafer-sort test data. Statistical post-processing (SPP) has successfully separated many of the effects of defects from...
Proceedings Papers

ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 359-364, November 14–18, 1999,
...Abstract Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 322-324, November 15–19, 2020,
... an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 345-351, November 15–19, 2020,
... chain diagnosis requires failing masking patterns to identify faulty chains and their fault types for designs with test compression. In other words, it cannot diagnose the chain failures which don't fail the masking chain patterns. Unfortunately, advanced FinFET technologies with more manufacturing...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 533-536, November 9–13, 2014,
... Design and Test course in the master program Electrical Engineering and Information Technology at the University of Applied Sciences in Rosenheim. The labs include an introduction to a HILEVEL Griffin III test system, creation of pin and test setup, the import of vector files from verification test...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 585-594, November 14–18, 2004,
...Abstract Abstract Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. While regular raster and special cache patterns (i.e. weak-write test mode) detect...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 188-197, November 15–19, 2020,
... manufacturing costs in comparison with the designing and testing of PCBs which still retains a large presence domestically. This offshoring of manufacturing has created a surge in the supply chain vulnerability for potential adversaries to garner access and attack a device via a malicious modification. Current...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 198-201, November 13–17, 2011,
... no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 181-190, November 14–18, 2004,
...Abstract Abstract Since failure analysis (FA) tools originated in the design-for-test (DFT) realm, most have abstractions that reflect a designer's viewpoint. These abstractions prevent easy application of diagnosis results in the physical world of the FA lab. This article presents a fault...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 80-83, October 31–November 4, 2021,
... method that combines design for test (DFT) features, direct bitcell access (DBA), and nondestructive fault isolation techniques. With examples and case studies, it is shown how the approach makes use of electrical failure analysis data to greatly reduce the cycle time of root cause identification...
Proceedings Papers

ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 318-321, November 9–13, 2014,
...Abstract Abstract The case study in this paper describes how collaboration between customer design and test teams and a thorough FAB investigation triggered by a detailed electrical analysis using the Atomic Force Nanoprober (AFP) resulted in the effective resolution of a challenging implant...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 35-41, November 1–5, 2015,
...Abstract Abstract Laser Voltage Probing (LVP) using continuous-wave near infra-red lasers are popular for failure analysis, design and test debug. LVP waveforms provide information on the logic state of the circuitry. This paper aims to explain the waveforms observed from combinational...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 459-464, November 11–15, 2001,
...Abstract Abstract The ongoing challenge of test is to obtain high quality at a reasonable cost. Increasing design complexity, signal integrity, and power issues mean that design-for-testability (DFT) and design-for-diagnosibility (DFD) can no longer be treated as an add-on. Similarly, serious...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 352-356, November 15–19, 2020,
...Abstract Abstract Many fabless customers do not share the design information such as LEF/DEF (Library Exchange Format and Design Exchange Format), design netlist, and test program information with foundries because they contain proprietary IP. Determining the root-cause of defects...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 270-274, November 4–8, 2007,
... structures, allows experiments to be completed more quickly providing much faster cycles of learning. Two different test structures are described. The first one was designed for other purposes but was adopted for silicide pipe detection at M1. The second was specially designed and allows pipe detection...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 332-337, November 14–18, 2010,
.... There are 24 IO pins and 30 test cycles involved in the pattern. Generally, four different states are present in a test pattern, namely high ( 1 low ( 0 pass ( P ) or don t care ( X). The high and low inputs toggle according to the logical functions the device is designed to perform. The pass states represent...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 419-422, November 12–16, 2006,
... logic circuits of complex hierarchical design. Scan chain diagnostics to pinpoint the failing scan latch logic circuit following ABIST testing frequently results in ever greater uncertainty; increased number of suspect circuits related to the failure. A case study analysis successfully applied...