This study responds to our need to optimize failure analysis methodologies based on laser/silicon interactions, using the functional response of an integrated circuit to local laser stimulation. Thus it is mandatory to understand the behavior of elementary devices under laser stimulation, in order to model and anticipate the behavior of more complex circuits. This paper characterizes and analyses effects induced by a static photoelectric laser on a 90 nm technology PMOS transistor. Comparisons between currents induced in short or long channel transistors for both ON and OFF states are made. Experimental measurements are correlated to Finite Elements Modeling Technology Computer Aided Design (TCAD) analyses. These physical simulations give a physical insight of carriers generation and charge transport phenomena in the devices.

Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require backside sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces will typically use conventional Laser Chemical Etching (LCE) platforms. The focus of this analysis will be to investigate and conjoin previously published techniques to this local preparation by using a combination of laser sources. A Continuous Wave (CW) and Pulse laser will be used at various processing stages to de-process IC packaging materials silicon and mold compound encapsulation.

This paper presents a study about the invasiveness of 1340 nm continuous wave laser used for electrical failure analysis on 28 nm advanced technologies. It underlines the potential laser-induced degradation for deep submicron technologies that could jeopardize analysis results by modifying physical and chemical properties at substructure level. The impact of laser power on transistor morphology and electrical behavior is studied and the results of this study enable us to setup safe experimental conditions.

The scope of this work is to investigate the timing characteristics of a state of the art fully functional IC through continuous wave (CW) and pulsed laser stimulation. The propagation delay of a gate depends on the drain current of nMOS and pMOS transistors, load capacitance and supply voltage. Localized photocurrent induced by laser beam alters some of these electrical characteristics, resulting in a change in the switching time of the gate. In addition to the desired local timing influence, a global effect on the timing throughout the full scanning period occurs as secondary phenomenon that - if not taken into account properly, may mask the local signal. This effect is strong under CW laser operation and can be drastically reduced in pulsed laser condition.

Laser-voltage probing (LVP) and imaging (LVI) using a continuous-wave (CW) 1320-1340nm laser have become mainstream techniques for electrical fault isolation. A 1064nm laser with a 20% shorter wavelength offers immediate resolution advantages compared to 1320nm at a cost of increased intrusion. This paper explores the potential of CW 1064nm laser and identifies opportunities in fault isolation

A spectroscopic photon emission microscope (SPEM) which is capable of high resolution spectroscopy for a continuous wavelength range between 300 nm to 1700 nm has been developed. Photon emissions were observed at energy levels below silicon bandgap from pn junctions and MOSFET devices at different biases. The experimental results indicate significant emission activity in this range. It was also found that the spectra is closely correlated to the electric fields present in the devices.

A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.

The requirements for focused ion beam (FIB) systems to provide higher image resolution and machining precision continue to increase with the continuation of Moore’s Law. Due to the shrinking geometry and increasing complex structures and materials, it is ever more critical to scale the entire ion probe. The necessity for comprehensive analysis of the ion beam profile and understanding how the ion beam current distribution profile influences different aspects of nanomachining are becoming increasingly important and more challenging.

Recent developments and improvements of laser probing techniques are a good complement to traditional techniques like emission microscopy (static and dynamic) or laser stimulation (also static and dynamic, based on thermal or photoelectric stimulus) for the investigation of failure analysis and diagnostic of integrated circuits. Laser probing techniques have in fact evolved from mainly pulsed approach with high bandwidth [1] to other methodologies based on Continuous Wave (CW) [2,3,4,5]. The bandwidth of these CW approaches is generally lower than pulsed techniques and fine characterization of rising and falling edges or measurement of very small timing shifts can be more difficult or not possible for high speed devices. This bandwidth limitation is most of the time due to the amplification chain. But, CW probing bandwidth is good enough, and continuously improving, to identify directly or indirectly timing issues and to identify bad digital or analog behavior. The setup is also much easier than pulsed laser systems which require complicated synchronization between the system timebase and the device. On this other side new internal analysis modes have been introduced with for example some mapping mode based on frequency analysis or on timing degradation identification through second harmonic analysis [6,7]. At the same time these techniques have pushed the capabilities of a lot of existing tools to investigate low current, low voltage and/or low frequency devices such as analog parts, transmission gates and configurations when the defect cannot be activated at normal or high voltage. Comparison with EMission MIcroscopy (EMMI) in dynamic mode, which can have the higher bandwidth [8] is then possible.

With the 14nm technology node becoming a reality at today's state-of-the-art semiconductor manufacturing plants and the 10nm node actively being planned for, device structures have shrunk well beyond the minimum conventional transmission electron microscope (TEM) sample thickness: 50-100nm. This paper addresses the challenges in TEM sample preparation of sub 22nm three-dimensional test structures. As semiconductor device technology continues to shrink and become more complicated with the addition of three-dimensional device integration, unique sample preparation challenges will continue to arise. This opens the door to novel solutions for these problems like the one presented in this paper: an issue that arose where TEM projection effects interfered with proper characterization of a finFET test structure.

A modulated laser beam in the form of a continuous pulse train is explored on Laser Assisted Device Alteration (LADA). We term this pulsed-LADA to differentiate from conventional continuous wave (cw)-LADA. It is found that a duty cycle of less than 0.9 at low frequency above 1 kHz is sufficient to experience significant enhancements in laser stimulation. Following this, a new derivative of LADA technique called Electrically-enhanced LADA (EeLADA) is developed. Experimental results to demonstrate its capability in improving diagnostic resolution and potential application to hard failure debug will be presented.

A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.

Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

Dynamic Laser Stimulation using Continuous Wave (CW) Lasers has been a very important technique in fault isolating soft failures due to process defects and design speed paths in microprocessors. However, the rapid scaling down of the process technologies and the high density of logic laid out in silicon has made it difficult to precisely fault isolate using a conventional continuous wave laser which has a laser spot size of about ~300nm. Also, the remnant effects of a CW laser DLS like banding due to n-well interactions make it further difficult to achieve high resolution fault isolation. In this paper we discuss how by using a modulated pico-second pulsed laser, a DLS suspect is isolated to cell internal nets, which using a CW laser spanned across multiple cells. This is achieved by modulating the pulsed laser using an Electro-optical modulator and restricting the stimulation to only those parts of a test-pattern where the signal propagation occurs. Also, by synchronizing the pulsed laser with the clock of the test-program and changing the laser pulse delivery in time, high stimulation levels were achieved without being invasive. This revealed extra data points (DLS sites) that can help with making precisely accurate Physical FA plans that reduce turnaround time and also ensure high success rates. Specifically, in the case of a bridging defect between two nets wherein DLS sites were only seen on the victim net using conventional CW laser, the time resolved pulsed laser revealed DLS sites on the aggressor net as well. This confirmed the bridging between the two nets since the aggressor net was not electrically connected with the victim net. We discuss in detail how the DLS sites play their role in framing the perfect Physical FA plan. A detailed study of the resolution achieved using time resolved pulsed laser and its comparison with the same using a CW laser is shown on 14nm FinFET technology.

Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.

Integrated-circuit device dimensions continue to shrink, enabling higher density of devices and smaller node size. A number of strategies to improve the resolution of failure analysis and fault isolation tools exist, but some of these techniques are reaching fundamental limits so that engineers are also challenged to innovative methods to increase the useful life of existing toolsets. Laser Scanning Microscopy including Laser Voltage Probing and frequency mapping struggle to maintain resolution commensurate with shrinking feature size. Here we present two methods to improve efficiency and capability of this toolset using existing optical hardware and configuration. The first method applies a frequency mapping technique using scan chain data patterns that allow for data manipulation. This enables an effective resolution increase through deconvolution of data collected in a sequence of scans completed on varied device states. A second method using multiple triggers per loop to evaluate a deterministic continuous wave signal is shown to reduce probe acquisition time, improve job throughput time, and enable, better signal-to-noise ratio for common scan chain debug workflow.

Integrated circuit complexity and density are continuously increasing with the rapid progress of advanced technology nodes. The density of wafer acceptance test (WAT) pattern is also becoming higher as the device continuing to shrink. Failure analysis (FA) techniques have been developed to improve the precision of defect isolation. A technique with more precise fault isolation capability is needed when the test pattern density increased. In this paper we have isolated faults within a dense high Rc array by using conductive atomic force microscopy (C-AFM). The fault sites in the array can be located efficiently with nano-scale precision. Point contact I-V measurements provide a quantitative comparison of the fault sites.

The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is < 5 µm.

As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.