Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices [1-4]. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image [5-7]. Unlike topographical imaging, the C-AFM requires the probe tip to be coated with a conductive layer in order to pick up the electrical signals from the device under test. The coating needs to be sufficiently thick as it would wear off after a certain amount of physical scanning. This additional coating on the AFM tip is essential but poses a limit to the tip radius curvature. The commercially available tip radius is approximately 35nm (DDESP-10 from Bruker) and the dimension is too large for imaging of 20nm technology device. However, the limitation could be alleviated by subjecting the sample surface to treatment prior to C-AFM imaging. The aim of this surface treatment is to ensure C-AFM tip maintains sufficient scanning contact with the tiny conductive (tungsten) structure of the sample in order to achieve distinct current image. The surface treatment is done by creating a receding Inter-Layer Dielectric (ILD) from its neighboring tungsten contact. The creation of the receding depth could be achieved by either wet etching or dry etching (Reactive Ion Etching, RIE). In this work, the surface treatments by these two methods have been investigated and the recipe is optimized to obtain a clear current image. The optimized recipe is then applied on actual failure analysis where three cases are studied.

As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

Conductive Atomic Force Microscopy (C-AFM) is a useful tool for both electrical failure analysis (EFA) and physical failure analysis (PFA). In this paper, the root cause of a physical failure in an analysis image was verified from the evidence of two-dimensional AFM profile depth measurement. The other analysis technique, which is electrical parameter extraction by contacting I-V spectroscopy measurement, was also utilized to locate the possible defects. As a result, the failure mechanism was illustrated with an AFM topography image, which showed the silicon surface profile after removal of cobalt salicide (self-alignment silicide) by dilute HF. The vertical junction leakage path was identified with a C-AFM image.

Identifying defects in marginally failed vias has long been a challenge for failure analysis (FA) of state-of-the-art semiconductor integrated circuits. This paper presents two cases where a conventional FA approach is found to not be effective. The first case involves high resistance or marginally open vias. The second case involves early breakdown of large capacitors. The large size of the capacitor and the lack of ways to track electrical flow during diagnosis made it difficult to isolate the defect. The paper shows that conducting atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are effective techniques for isolation of via-related defects. The SCM technique could be applied to samples without a direct conducting path to the substrate, such as SOI samples. On the other hand, C-AFM allows current imaging as well as I-V characterization whenever a direct conductive path is available.

In this work, we introduce Conducting Atomic Force Microscopy (C-AFM) as a novel technique for the determination of the local effective electrical oxide thickness with a lateral resolution of a few nanometers and a thickness resolution in the sub ångström range. In this technique the conductive tip of an AFM, which is in mechanical contact with the bare oxide surface, is used as metal electrode to define a local MOS structure with nanometer lateral extension. Oxide thickness determination is done by fitting the local I-V curves to the well known Fowler Nordheim tunneling equation with a thickness sensitivity in the sub-ångström range. In addition, tunneling current images at constant applied voltage can be obtained simultaneously to the oxide surface topography. We present a scheme which allows the conversion of the tunneling current images into maps of the local electrical oxide thickness. Several examples demonstrate the versatile and far-reaching application of C-AFM to R&D and failure analysis.

Integrated circuit complexity and density are continuously increasing with the rapid progress of advanced technology nodes. The density of wafer acceptance test (WAT) pattern is also becoming higher as the device continuing to shrink. Failure analysis (FA) techniques have been developed to improve the precision of defect isolation. A technique with more precise fault isolation capability is needed when the test pattern density increased. In this paper we have isolated faults within a dense high Rc array by using conductive atomic force microscopy (C-AFM). The fault sites in the array can be located efficiently with nano-scale precision. Point contact I-V measurements provide a quantitative comparison of the fault sites.

This paper describes gate oxide defect localization and analysis using passive voltage contrast (PVC) and conductive atomic force microscopy (C-AFM) in a real product through two case studies. In this paper, 10% wt KOH was used to etch poly-Si and expose gate oxide. In the case studies, different types of gate oxide defects will cause different leakage paths. According to the I-V curve measured by C-AFM, we can distinguish between short mode and gate oxide related leakage. For gate oxide leakage, KOH wet etching was successfully used to identify the gate oxide pinholes.

Conducting Atomic-Force Microscopy (C-AFM) has a strong potential for the characterization of thin silicon oxides on the nanometer scale. Here we consider difficulties and possible errors that may arise during C-AFM experiments. Using electrostatic simulations it is shown that very sharp tips can cause an inhomogeneous electric field distribution leading to an error in the measured Fowler-Nordheim (FN) current. Further, it is found that a water film, which is ever present under ambient conditions, on the one hand homogenizes the electric field distribution but on the other hand decreases the resolution of the measurements. For increased oxide thickness this water film leads to a ring formation in the electric field maximum and therefore makes an interpretation of FN current maps difficult. The occurrence of protrusions after the applying of voltage pulses and voltage ramps to the sample is investigated by comparing experiments under ambient conditions with measurements in ultra high vacuum (UHV). From this comparison we can conclude that the observed protrusions are real topographic effects, when a water film is present on the surface. However, for UHV experiments on a baked sample it is not yet clear if the protrusions are due to charging effects or due to a reaction with a residual amount of water.

Voltage contrast (VC) is a useful technique and used widely in failure analysis of integrated circuit (ICs). This paper will demonstrate different FIB current intensities in a specific VC case and, by means of the technique, locate possible defect sites quickly. With the help of conductive atomic force microscopy (C-AFM), we can get an electrical verification at the same time. We discuss the relationship of VC and C-AFM as well as what the root cause of failure is in this case.

In this work a procedure is presented to look beneath the surface of a SiO2 film and to study the impact of the SiO2/Si interface morphology on the tunneling current, with high lateral resolution, by use of combined Conductive Atomic Force Microscopy (C-AFM) and Intermittent-Contact AFM (IC-AFM) measurements. Evidence is given that interface structures do have direct influence on the distribution of high current spots in MOS capacitors.

This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

A method to differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short defect in real products by analyzing the I-V curves acquired by Conducting-Atomic Force Microscopy (C-AFM) is presented. The method allows not only the correct short path to be identified, but also allows differentiation of gate-to-S/D GOS from non-GOS problems, which cannot be reached by passive voltage contrast (PVC) only.

As device dimensions continue to shrink, process defects tend to become more subtle. For most failure analysis (FA) studies, it is important to identify the defect location for the subsequent material analysis. To achieve this, nano-probing has been widely used in the FA community. Copper (Cu) contacts posed a significant challenge to nano-probing since Cu is soft and tends to deform during measurements. In addition, Cu oxidizes quickly in air, increasing contact resistance significantly between the probes and devices. This paper introduces electroless cobalt (Co) plating on Cu contacts for nano-probing to overcome these technical problems. As Cu is soft and oxidized quickly in air, the technique presented in this paper provides a technical solution for nano-probing on Cu contacts. With carefully characterized Co plating time, this technique can be used not only on Cu contacts but also on Cu interconnection.

Conventional isolation techniques, such as Optical Beam Induced Resistance Change (OBIRCH) or photoemission microscopy (PEM) frequently fail to locate failure points when only applied to power pin of the semiconductor device. In this paper, a novel OBIRCH failure isolation technique is utilized to detect leakage failures. Different test conditions are presented to identify the differences in current when all input pins are pulled high in an OBIRCH system. In order to verify a failure point, it is necessary to perform electrical analysis of the suspected failure point in the failing sample. In general, Conductive Atomic Force Microscope (C-AFM) and a Nano-Prober is sufficient to provide the electrical data required for failure analysis. Experiment results, however, prove that this novel OBIRCH failure isolation technique is effective in locating the failure point, especially for leakage failures. The failure mechanism is illustrated using cross-sectional TEM.

Dielectric film quality is one of the most important factors that will greatly impact device performance and reliability. Device level electrical analysis techniques for dielectric quality monitoring are highly needed. In this paper we present results using a new electrical AFM mode, scanning Microwave Impedance Microscopy (sMIM), for characterization of device oxide quality and for fault isolation. Devices with poor oxide quality show sMIM nano C-V and dC/dV hysteresis behavior during forward and reverse bias sweep. The sMIM capacitance sensitivity is below 1 aF allowing one to capture C-V spectra from the MOS structure formed by the gate and gate oxide with excellent signal/noise ratio and observe subtle variations between different sites.

The use of Atomic Force Microscopy (AFM) electrical measurement modes is a critical tool for the study of semiconductor devices and process development. A relatively new electrical mode, scanning microwave impedance microscopy (sMIM), measures a material’s change in permittivity and conductivity at the scale of an AFM probe tip [1]. sMIM provides the real and imaginary impedance (Re(Z) and Im(Z)) of the probe-sample interface. By measuring the reflected microwave signal as a sample of interest is imaged with an AFM, we can in parallel capture the variations in permittivity and conductivity and, for doped semiconductors, variations in the depletion-layer geometry. An existing technique for characterizing doped semiconductors, scanning capacitance microscopy, modulates the tip-sample bias and detects the tip-sample capacitance with a lock-in amplifier. A previous study compares sMIM to SCM and highlights the additional capabilities of sMIM [2], including examples of nano-scale capacitance-voltage curves. In this paper we focus on the detailed mechanisms and capabilities of the nano-scale C-V curves and the ability to extract semiconductor properties from them. This study includes analytical and finite element modeling of tip bias dependent depletion-layer geometry and impedance. These are compared to experimental results on reference samples for both doped Si and GaN doped staircases to validate the systematic response of the sMIM-C (capacitive) channel to the doping concentration.

The oxide-nitride-oxide (ONO) is one of the critical layers in the deep trench (DT) capacitor of the modern DRAM structure. This paper highlights a ONO inspection methodology, which used the silicon wet etching to enhance the ONO leakage point. First, a hole was milled nearby the leakage ONO, which was localized by using focused ion beam (FIB). Then, silicon was removed by an etching solution from the opening. When the poly of DT is etched through the ONO weak point, the leakage site will be enhanced. With the silicon wet etching enhancement, the ONO leakage point is easy to be observed by X-S FIB inspection. The real ONO leakage point is useful information for the root cause finding and the process improvement.

Many of the standard techniques of Failure Analysis (FA) are breaking down or becoming less useful as feature sizes drop below 100nm. The tenth micron milestone appears to be a fundamental limitation to many common techniques. Use of Current Image-Atomic Force Microscopy (CI-AFM) combined with Atomic Force Probing (AFP) brings about a combination of technologies, which allow for extension of FA below the nano-scale.

This presentation provides an introduction to atomic force microscopy (AFM) and its many uses in semiconductor failure analysis. It provides examples showing how AFM is used to obtain information on electric fields, surface potential, current, resistance, capacitance, impedance, carrier concentration, mechanical contact (height and energy dissipation), temperature, and composition. It also addresses a number of related issues including the use of external stimuli, sample preparation requirements, and probe tip selection.

In this paper, we focus on how to identify non-visual failures by way of electrical analysis because some special failures cannot be observed by SEM (scanning electron microscopy) or TEM (transmission electron microscopy) even when they are precisely located by other analytical instrumentation or are symptomatic of an authentic or single suspect. The methodology described here was developed to expand the capabilities of nano-probing via C-AFM (conductive atomic forced microscopy), which can acquire detailed electrical data, and combining the technique with reasoned simulation using various mathematic models emulating all of the significant failure characteristics. Finally, a case study is presented to verify that such defect modes can be identified even when general PFA (physical failure analysis) cannot be implemented for investigating non-visual failure mechanisms.