Abstract This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells. Despite the high aspect ratio of the region of interest, the method can resolve offsets down to a few nm. Such precision is critical, as the paper explains, because the radius and thus electrical characteristics of each memory cell is determined by the etching angle.

Abstract This paper presents a method for determining positional variation and offsets in high aspect ratio etches used in the production of 3D NAND devices. The method uses a 3D fiducial as a positional reference in the field-of-view, which not only allows for high precision tracking of features through the depth of the device, but also aids in the alignment of images when performing 3D reconstructions. The workflow is based on plasma dual beam diagonal milling, which allows users to characterize structures through the device stack at a much higher throughput/slice than conventional methods, enabling enhanced process monitoring and control.

Abstract The importance of understanding mismatched behavior in SRAM devices has increased as the technology node has shrunk below 100nm. Using the nanoprobe technique [1-3], the MOS characteristics of failure bits in actual SRAM cells have been directly measured. After transistors that are failing were identified, the best approach for identifying nanoscale defects was determined. In this study, several types of nanoscale defects, such as offset spacer residue, salicide missing from the active area, doping missing from the channel, gate oxide defects, contact barrier layer residue, and severed poly-gate silicide were successfully discovered.

Abstract This paper outlines a methodology which accurately identifies fault locations in Mixed Signal Integrated Circuits (ICs). The architecture of Mixed Signal ICs demands more attention during failure analysis because of the complexity of measuring both the analog and digital signals in a compact circuit. In this paper, the GHz range of data signal or radio frequency (RF) signal from an internal IC circuit will be extracted by a high-impedance active single probe in order to find the internal IC circuit failure locations. The advantages of using a single probe is that it can maneuver to extract data almost anywhere in the circuit, providing ranges of bandwidth in GHz with no loading effect on the circuits during measurement. The process of preparing a sample and extracting a signal will be described.

Abstract Electron Beam Induced Current is a powerful tool for Scanning Electron Microscopy (SEM) imaging mode. In this paper, the history and evolution of this technique are discussed. Some important defects are presented as well as their technological interpretation. A new custom amplifier is presented and its implementation in Time Resolved EBIC (TREBIC) is also proposed, the main differences with EBIC are pointed out.

Abstract A system-on-chip processor (90 nm technology node) was experiencing a high basic function failure rate. Using a lab-based production tester, laser assisted device alteration, nanoprobing, and physical inspection; the cause of failure was traced to a single faulty P channel transistor. The transistor had been partially subjected to N doping due to poor photo-resist coverage caused by halation.

Abstract The presence of crystalline defects, including dislocations and pipeline defect, is detrimental to both the processing and the intrinsic quality of semiconductor devices. The electrical parametric or functional failures generated by those defects require accurate identification and proper classification in a continuous improvement mindset. Depending on the failure analyst choice of the investigation technique, the distinction between a dislocation and a pipeline defect can be difficult. In this paper, based on case studies of mixed-mode devices, the various electrical and physical FA investigation techniques are explored and compared. From an electrical investigation standpoint, fault localization techniques will be reviewed (Thermal Laser Stimulation and Photon Emission Microscopy) as well as the direct electrical measurements means (external measurement and nanoprobing AFP). From a physical analysis standpoint, the use of various methods after deprocessing will be considered: top down delineation etch, Atomic Force Microscopy (AFM), Scanning Microwave Microscopy (SMM), and Transmission Electron Microscopy (TEM). The position of the defect as well as its physical signature observed through the various methods will determine its proper classification and will determine the appropriate corrective actions. The paper will be concluded with a discussion on the physical differences between a dislocation and a pipeline defect, as well as insights into the wafer fab manufacturing process.

Abstract Fluid ejection systems fabricated using MEMS (microelectromechanical systems) technology have a wide variety of applications ranging from ink jet thermal printing [1] to drug delivery for medical applications [2]. Microfluidic MEMS drop ejectors accurately control the volume and velocity of fluid dispensed. For the electrostatic drop ejector to function properly, the fluid must be contamination free, inert to the MEMS components and inert to materials and epoxies used for packaging. This paper will discuss the failure mechanisms and analysis techniques used to diagnose root cause(s) of failure in as-fabricated (unreleased) drop ejectors, and released, packaged drop ejectors tested in both air and water. Corrective actions implemented to mitigate the failure mechanisms and improve performance and reliability at both the wafer/die level and packaged level will be discussed.

Abstract This article analyzes the cause of Vcc shorts in advanced microprocessors. In one instance, an advanced microprocessor exhibited Vcc shorts at wafer sort in a unique pattern. The poly silicon was narrow in one section of the die. The gates were shown to measure small, but no electrical proof of the short could be seen. To prove the short existed as a result of the narrow gate, a Scanning Capacitance Microscope (SCM) was utilized to confirm electrical models, which indicated a narrow poly silicon gate would result in Vcc shorts. High frequency dry etching and UV-ozone oxidation were employed for deprocessing. The use of the SCM confirmed the proof that the Vcc shorts were caused by narrow gate length which causes its leaky behavior. This conclusion could have only been confirmed by processing of material through the wafer foundry at the cost of money and time.

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the backside of the device as a means of locating metallization defects on state of the art bulk silicon and SOI based microprocessor technologies. It builds on previous work which focused only on flip-chip SOI samples. This paper will demonstrate additional EBAC techniques and the ability to analyze devices processed in bulk silicon technology. Also included are the results obtained from an SOI device mounted in a non flipchip package type. Additional details related to sample preparation, equipment used, and improved practices are described.

Abstract The use of analog blocks in deep submicron intergrated circuits has become commonplace. The process used for these circuits is tuned for pure digital applications. Thus, identification of failures in these blocks requires a detailed understanding of the design, test, and process not previously done with digital failure analysis. This paper will detail the method, results, and solution to a silicided related integral non-linearity in a deep submicron 10-bit DAC.

Abstract This paper discusses the development of an automated cell layer counting process for preparing 3D NAND flash memory samples for TEM analysis. In an initial proof-of-concept, several line markings were inscribed on the test device in evenly spaced intervals in order to evaluate its helpfulness for a human operator. A more automated procedure was then developed in which cell layers were counted to a desired target layer starting from a reference layer set by the operator. At that point, the operator could begin preparing the TEM sample.

Abstract Secondary electron signal is widely used in Focused Ion Beam (FIB) systems for imaging and endpointing. In the application of integrated circuit modification, technology has progressed towards smaller dimensions and higher aspect ratios. Therefore, FIB based circuit modification processes require the use of primary ion beam currents below 10 pA and Gas Assisted Etching (GAE). At low beam currents, short pixel dwell times and high aspect ratios, the level of available secondary electrons for detection has declined significantly. FIB GAE and deposition requires delivery and release of a gaseous agent near the beam scanning area, and involves insertion of a gas delivery nozzle made of conductive material and grounded for charge prevention purposes. The proximity of a grounded gas delivery nozzle to the area being milled and/or imaged creates a “shielding” effect, further lowering secondary electron signal level. The application of a small positive bias to the gas delivery nozzle provides an effective way of reducing the “shielding” effect. Depending on the geometrical arrangement of the gas delivery system and other conductive objects in the chamber, an optimized nozzle bias potential can create conditions favorable for enhanced extraction and collection of secondary electrons. The level of the secondary electron image signal, collected in an FEI Vectra 986+ system, from a grounded copper sample with the nozzle extended and biased can be enhanced as much as six times as compared to the grounded nozzle. Secondary electron intensity endpoint is improved on backside samples, however shielding of the nozzle field by the bulk silicon substrate limits the electron extraction effect from within a via. For front side edits the improvement of endpoint signal level can be dramatic. Lateral image offset induced by the electrostatic field of a biased nozzle, can be removed by software position compensation.

Abstract We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET on Strained Silicon on Insulator (S-SOI) substrates for the first time. The degradation has been found to be significantly higher for the S-SOI devices in comparison to SOI counterparts. Subsequent to a Constant Voltage Stress (CVS) during NBTI measurements, a negligible change in the subthreshold swing values was observed. Thus it is believed that generation of fixed charge is responsible for the observed BTI shift in threshold voltage (VTH) and transconductance (GM). Also higher BTI degradation was recorded for short channel devices.

Abstract Dynamic Laser Stimulation (DLS) techniques for Soft Defect Localization (SDL) have been well documented for logic devices [1][2]. More recent literature has broadened the traditional SDL pass/fail mapping by employing multiple device parameters including power analysis [3], spectrum response [4], and other analog variations [5]. A practical and efficient implementation of SDL without the use of synchronization or traditional Automatic Test Equipment (ATE) hardware is presented. A dynamic way of analyzing many parameters of mixed signal and analog ICs can be obtained through the use of a high waveform rate oscilloscope, feedback loop, or discrete comparator. Multiple case studies are shown to illustrate the methodology.

Abstract Stacked-die packaging was used to make an octal 20-bit analog-to-digital (A/D) converter by stacking two quad A/D converter die in a single 48-lead QFN (quad flat-pack, no leads) package. Reliability testing for product qualification initially failed only (biased) HAST test. Two failure mechanisms were identified. The first mechanism was silver ion migration at sensitive analog inputs due to high conductive die-attach fillets on the bottom die. The second mechanism was ILD delamination and passivation layer cracking due to spacer-attach stress on the surface of the bottom die. Electrical failure analysis was aided by a self test mode designed into the quad A/D converter. Package opening and other standard failure analysis techniques required some modification to accommodate the stacked-die package. This work points to critical stacked-die assembly steps, including conductive die-attach and nonconductive spacer-attach application, where effects of moisture, bias, and thermal stress must all be considered.

Abstract Visible light laser voltage probing (LVP) for improved backside optical spatial resolution is demonstrated on ultra-thinned samples. A prototype system for data acquisition, a method to produce ultrathinned SOI samples, and LVP signal, imaging, and waveform acquisition are described on early and advanced SOI technology nodes. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

Abstract The paper describes the approach that was developed to cope with the specific difficulties encountered with FIB circuit modification on the 0.5 and 0.35um technologies from a multitude of silicon vendors. This approach involves adaptations in FIB hardware (insulator deposition), software (image alignment), design practice (alignment marks, spare parts, routing recommendations) and FIB practice (procedure for node localisation and contacting, via drill and fill). The latter seems to be a major factor limiting FIB circuit repair feasibility: although it is perfectly feasible to drill deep and small vias (e.g. between minimum spacing overlying metallization), it is not evident to reproducibly fill such holes and obtain a good and reliable via resistance. This limits the minimum size of FIB vias to deep circuit nodes. The developed total approach enables to continue the use of FIB for circuit repair on the new generations of processes, with all the well-known benefits w.r.t. cost savings and Time-To-Market.

Abstract Circuit edit techniques have been developed for silicon-on-insulator (SOI) devices using a coaxial photon-ion column. Novel trenching, navigation and milling methods, utilizing sub pico-Amp beam currents provide enhanced capability for editing devices with decreased geometries including buried (Box) thickness. Flat trenches 200x200µm were obtained using real time optical fringe monitoring with 125nm accuracy with 950nm λ and FIB bit map milling to adjust for parallelism to the ILD0. This bit map milling technique controlled the etch rate to maintain trench flatness by correlating the optical fringes to the bit map grayscales to vary the dwell time of the ion beam across the trench floor. Through highly accurate, CAD directed beam deflection control, beam placement accuracy in the sub 20nm regime can readily be accomplished, sub pA beam currents provide ultracontrolled etch rates and high aspect ratio (HAR) capability. Complete process definitions, techniques and results are reported. These techniques have proven successful in circuit edit below 90nm, and are expected to meet future technology circuit edit requirements down to 45nm.

Abstract Visible light laser voltage probing (LVP) for backside improved optical spatial resolution is demonstrated on ultrathinned bulk Si samples. A prototype system for data acquisition, a method to produce ultra-thinned bulk samples as well as LVP signal, imaging, and waveform acquisition are described on bulk Si devices. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.