The papers in this volume are based on presentations accepted for the 46th International Symposium for Testing and Failure Analysis, ISTFA 2020, that was scheduled to be held from November 15 to 19, 2020, in Pasadena, California, USA. The conference was cancelled due to the coronavirus (COVID-19) pandemic.

Listings of the EDFAS 2001-2002 Board of Directors, the ISTFA 2001 Organizing Committee, and other contributors and committee members.

Listings of the ISTFA 1997 Organizing, Steering, Abstract Review, and Workshop Committees and other contributors.

Listings of the EDFAS 1999-2000 Board of Directors, the ISTFA 1999 Organizing and Abstract Review Committees, and other contributors.

Listings of the EDFAS 2000-2001 Board of Directors, the ISTFA 2000 Organizing Committee, and other contributors and committee members.

Listing of the ISTFA 1996 Organizing Committee.

Listings of the ISTFA 1998 Organizing, Steering, Abstract Review, and Workshop Committees and other contributors.

Radiation-induced latchup sites in a high-performance commercial application-specific integrated circuit (ASIC) manufactured in a bipolar gate array have been identified using a photoemission (PE) microscope before and after isolating individual circuit elements with a focused ion beam (FIB) system. Latchup sites were determined to be associated with grounded unused resistors and transistors in an emitter-coupled logic (ECL) input buffer. Simulation of the oxide isolation scheme confirmed the presence of pnpn structures at the likely latchup sites. A corrective action to redesign the layouts to disconnect unused resistors and transistors resulted in successful elimination of latchup in the ECL buffers.

Modern electronic systems rely on components with nanometer-scale feature sizes in which failure can be initiated by atomic-scale electronic defects. These defects can precipitate dramatic structural changes at much larger length scales, entirely obscuring the origin of such an event. The transmission electron microscope (TEM) is among the few imaging systems for which atomic-resolution imaging is easily accessible, making it a workhorse tool for performing failure analysis on nanoscale systems. When equipped with spectroscopic attachments TEM excels at determining a sample’s structure and composition, but the physical manifestation of defects can often be extremely subtle compared to their effect on electronic structure. Scanning TEM electron beam-induced current (STEM EBIC) imaging generates contrast directly related to electronic structure as a complement the physical information provided by standard TEM techniques. Recent STEM EBIC advances have enabled access to a variety of new types of electronic and thermal contrast at high resolution, including conductivity mapping. Here we discuss the STEM EBIC conductivity contrast mechanism and demonstrate its ability to map electronic transport in both failed and pristine devices.

Bipolar silicon transistors were exposed to Californium (252Cf) radiation and neutron radiation obtained from nuclear facilities. The effect of the radiation on the transistors was measured by recording the transistor's electrical characteristic as a function of radiation fluence. Correlation between Californium (252Cf) -induced and neutron-induced damage and previously published data for proton-induced radiation damage was made. Finally, the effect ofthenna1 annealing on gain recovery was also investigated.

This paper describes a new technique for identifying defects on integrated circuit. This technique detects the noise content in light emitted from defect sites. The purpose of this technique is to determine which of many light emission sites represent a defect and which represent normal devices. It reports the first phase of studies to evaluate the feasibility and potential effectiveness of this technique. The feasibility of this technique has been demonstrated by simultaneously monitoring electrical noise and the noise in the light emitted from a gallium arsenide light emission diode (LED) and a bipolar transistor. The paper will present the methodology and apparatus used to detect and analyze the noise in light emission.

Single probe beam phase-sensitive detection has been applied to backside optical probing using an interferometer with a novel vibration cancellation scheme. Improved waveform quality and consistency, compared to amplitude-sensitive detection, has been successfully demonstrated on a number of CMOS microprocessors based on the 0.18 um logic process technology. The interferometric probing scheme will be described in detail and results will be presented.

Listings of the ISTFA 2012 User Groups, Moderators, and Presenters.

Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.

The temperature and strain rate effects on the shear properties of selected Pb-free solders were investigated. The experiments were performed using single lap shear specimens. All testing was performed using a standard tensile test metrology. The following results were found: 1) Sn-3.5 wt.% Ag outperformed all the other solders in terms of its mechanical strength at all test conditions due to the formation of Ag3Sn precipitates in the bulk solder and Cu6Sn5 intermetallic formation along the interface. However, ductility was sacrificed as this solder strain hardens. 2) The strength and ductility of the solder joint is strongly dependent on the test temperature and strain rate. Data in this work reflects a decrease in strength and ductility when the test temperature is increased. This phenomenon can be attributed to the increase in energy as temperature is increased to overcome dislocation barriers such as impurities and grain boundaries that impede the motion of dislocation. When strain rate is increased, the amount of plastic deformation experienced by the solder increases and more dislocations are formed. Due to the increase in proximity and number of the dislocations, the net result is that motion of the dislocations are hindered thus requiring more stress to deform the material.

The continuing evolution of semiconductor packages to finer solder ball pitches, shrinking solder ball volume, and new solder materials, mandates the availability of methods to accurately assess solder joint reliability both at the component and at the board level. Many tests in use for this purpose cannot provide direct measurements of solder joint interfacial strength. This paper reports on the investigation of laser spallation for interfacial strength assessments and understanding of failure mechanisms on chip scale package (CSP) solder joints.

This article describes a novel way to prepare TEM samples from existing FIB lift out samples for third dimensional observation. An in situ needle in a FIB column is applied to handle the sample and a special sample holder is used that tilts the sample rapidly to 90º in the FIB column. The application of this technique is also discussed.

The acquisition of reliable Acoustic Micro Images (AMI) are an essential non-destructive step in the Failure Analysis (FA) of electronic packages. Advanced packaging and new IC materials present challenges to the collection of reliable AMI signals. The AMI is complicated due to new technologies that utilize an increasing number of interfaces in ICs and packages. We present two case studies in which it is necessary to decipher the acoustic echoes from the signals generated by the interface of interest in order to acquire trustworthy information about the IC package.

In this work we present a new defect localization capability on Wafer Level Chip Scale Packages (WLCSP) with small-scale Cu pillars using advanced 3D X-ray microscopy (XRM). In comparison to conventional microcomputed tomography (Micro-CT or microCT) flat-panel technology, the synchrotron-based optically enhanced 3D X-ray microscopy can detect very small defects with submicron resolutions. Two case studies on actual failures (one from the assembly process and one from reliability testing) will be discussed to demonstrate this powerful defect localization technique. Using the tool has helped speed up the failure analysis (FA) process by locating the defects non-destructively in a matter of hours instead of days or weeks as needed with destructive physical failure analysis.

Presentation slides for the ISTFA 2023 Tutorial session “Fundamental Considerations in the Justification, Design, and Construction of an Analytical Laboratory for High Tech Imaging and Processing Tools.”