Abstract Dynamic Laser Stimulation using Continuous Wave (CW) Lasers has been a very important technique in fault isolating soft failures due to process defects and design speed paths in microprocessors. However, the rapid scaling down of the process technologies and the high density of logic laid out in silicon has made it difficult to precisely fault isolate using a conventional continuous wave laser which has a laser spot size of about ~300nm. Also, the remnant effects of a CW laser DLS like banding due to n-well interactions make it further difficult to achieve high resolution fault isolation. In this paper we discuss how by using a modulated pico-second pulsed laser, a DLS suspect is isolated to cell internal nets, which using a CW laser spanned across multiple cells. This is achieved by modulating the pulsed laser using an Electro-optical modulator and restricting the stimulation to only those parts of a test-pattern where the signal propagation occurs. Also, by synchronizing the pulsed laser with the clock of the test-program and changing the laser pulse delivery in time, high stimulation levels were achieved without being invasive. This revealed extra data points (DLS sites) that can help with making precisely accurate Physical FA plans that reduce turnaround time and also ensure high success rates. Specifically, in the case of a bridging defect between two nets wherein DLS sites were only seen on the victim net using conventional CW laser, the time resolved pulsed laser revealed DLS sites on the aggressor net as well. This confirmed the bridging between the two nets since the aggressor net was not electrically connected with the victim net. We discuss in detail how the DLS sites play their role in framing the perfect Physical FA plan. A detailed study of the resolution achieved using time resolved pulsed laser and its comparison with the same using a CW laser is shown on 14nm FinFET technology.

Abstract As semiconductor technology continues to advance to smaller dimensions and more complex circuit designs, it is becoming more challenging to locate the resistive short directly between two metal lines (signals) due to a metal bridge defect. Especially these two metal lines are very long and relevant to many functional modules. After studying the failed circuit model, we found there should be a tiny leakage between one of the bridged signals and one of common power signals (such as VDD and GND) on a failed IC compared with the reference one, if there is a metal bridge defect between these two bridged signals. The tiny leakage between one of the bridged signals and one of power signals is an indirect leakage that is a mapping of the direct resistive short between these two bridged signals. The metal bridge defect could be pinpointed with the tiny leakage between one of the bridged signals and one of power signals by Lock-in IR-OBIRCH. It is an easier and faster way to locate the metal bridge defects. In this paper, the basic and simple circuit model with a metal bridge defect will be presented and two cases will be studied to demonstrate how to localize a metal bridge defect by the tiny leakage between one of the bridged signals and one of power signals.

Abstract The aim of this paper is to present a typical bridge defect case inside digital circuitry, from diagnosis to emission point of view. Specific considerations have allowed to establish the exact point of failure. Keywords— bridge defect, aggressor and victim, region of intersection

Abstract As scaling-down of dynamic random access memory (DRAM) has been continued, the pitch of metal-line already reached sub-50nm where it is hard to define the soft bridge and normal one. Moreover, the metal bridge failure at system level cannot be corrected with in-situ system error-code correction (ECC) modules. In order to screen these failures in the wafer or/and package level electrical tests, high voltage stress methods are necessary. Therefore, accurate stress quantity decided by combination temperature, voltage and time, and effective stress methodologies are essential for high quality and reliability. For a mass production environment, a wafer level burn-in (WBI) can enable multiple word-lines simultaneously and consistently is appropriate. Moreover, we confirmed the actual voltage level on real cells in WBI and optimized stress parameters in terms of time and voltage. Finally, it was proven through the WBI evaluation for over 60k DRAM chips.

Abstract The bridge defect is one of the most difficult defects to locate. When classical static and dynamic optical techniques reach their limits, applying a dynamic signal on the power supplies for stimulating the defect allows obtaining useful additional information helping the localization. In this paper, we explore these techniques on a real case analysis of bridge defect in a scan chain on a 28nm technology node circuit. We will show that OBIRCH, LVI, static & dynamic EMMI do not give significant signatures for the defect localization. Finally we show that EMMI and LVI signatures applying a clock on the power supply bring relevant information to locate efficiently the defect.

Abstract For fault management, various types of error-correcting codes (ECC) have been widely used for most computers and memory. From a memory perspective, the ECC technique is generally adopted for DRAM modules to correct data corruption among multiple chips, not in-chip level. Recently, increased soft single-bit failures have accelerated introduction of the ECC technique into DRAM components. For reliability, fault generation technique by high voltage at high temperature, also known as burn-in stress, has been widely used in the IC manufacturing process. In DRAM, burn-in stress is also useful to screen latent defects or to predict device lifetime. In this paper, we studied un-correctable errors which occurred due to various types of storage node bridge defects in ECC DRAM. 12 faulty cells among 1,000 cells are observed after burn-in stress. Retention time of each cell is measured with automatic test equipment under the various temperature conditions, and activation energy were extracted from measurement results. Results of activation energy show that there were two types of faults, one was metal-metal hard bridge (0.14eV) and the other was dielectric-dielectric soft bridge (0.35eV), in comparison with normal cells (0.53eV). Moreover, soft bridge was carefully analyzed with TEM and nanoprobing showing that activation energy analysis was well-matched.

Abstract Gate-to-drain contact short issue in floating gate memory has been studied. Two cases will be discussed, floating-gate to drain contact short, and control-gate to drain contact short, both caused by leakage bridge defect. The abnormal electrical device characteristic combined with modeling gives further insight into the failure mode. Nano-prober measurement results not only provide an evidence of short-contact issue but also measures the current behaviors between drain and gate in floating gate configuration. These results help to predict the defect location and successfully monitor the bridge-failure through electrical analysis.

Abstract In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.

Abstract With the ever decreasing trend in accessibility to hardware tools, the need for software tools is becoming greater than ever for IC fault diagnosis. In this paper, we present a process of studying the limitations and capabilities of fault diagnosis using automated Diagnosis tools, such as FastScan™, as applied to a programmable, parallel processing DSP, The Multimedia Video Processor (TMS320C80). Starting with a brief description of the MVP, we describe how FastScan™ is integrated for supporting fault diagnosis. For establishing the effectiveness of FactScan™ as a diagnostic tool, both the simulation and manufacturing modes of evaluation were done. In simulation mode, both the fault model and the heuristics used by the fault diagnosis software are tested by inserting known defects using a focused ion beam (FIB), machine. This process is then repeated with unknown defects in unknown locations. Experiments on several chips demonstrate the value of the tool and its limitations in relation to detection of classic stuck-at faults and some realistic faults, such as bridging defects.

Abstract This paper places a strong emphasis on the importance of applying the correct FA approach in physical sample preparation to identify hidden defects that can be easily removed during analysis. A combination of mechanical parallel polishing and chemical etching was used during the sample preparation after electrical fault isolation. Such a combination is both effective and efficient in identifying the single Via punch-through from a sea of Via in MIM structure as well as finding the thin layer of barrier bridging under the Al metal. It serves as a quick way to verify any suspect without time consuming FIB progressive cuts at the hotspot location which sometimes turns out to be an induced spot with a defect located at other site due to the circuitry connection. It would serve as a good reference to wafer fab that encountered such issues.

Abstract This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

Abstract Bridging faults are a common failure mechanism in integrated circuits and scan-based diagnosis does a good job of isolating these defects. Diagnosis, however, can sometimes result in large search areas. Typically, these areas are caused by long repeater nets. When this happens, physical failure analysis will become difficult or impossible. This paper concerns itself with using a bridging fault analysis as a means of reducing these large search areas.

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Abstract Logic diagnosis analyzes scan test failures and produces a list of potential defect locations and types. This information is often used as a starting point for a detailed physical failure analysis (PFA) process that locates the actual physical defect. One important criterion that dictates whether PFA can be performed on a certain die is the physical area of the die over which the potential defect locations reported by diagnosis are spread. While logic diagnosis works with a logic-level abstraction of the design, in this paper we describe the use of additional design layout information during diagnosis to lead to better localization of defects and reduce the area over which potential defect locations are spread. This directly results in more die becoming suitable for PFA. We demonstrate the effectiveness of such “layout-aware” diagnosis for PFA using an industrial case study in which several die from two wafers were diagnosed and 61% and 78% more die became suitable for PFA using layout-aware diagnosis.

Abstract Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.

Abstract New process will introduce new failure mechanisms during microelectronic device manufacturing. Even if the same defect, its root causes can be different for different processes. For aluminum(Al)-tungsten(W) metallization, the root cause of metal bridging is quite simple and mostly it is blocked etch or under-etch. But, for copper damascene process, the root causes of metal bridging are complicated. This paper has discussed the various root causes of metal bridging for copper damascene process, such as those related to litho-etch issue, copper CMP issue, copper corrosion issue and so on.

Abstract By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.

Abstract The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

Abstract In this paper, a comprehensive study to find a memory related yield loss in 90 nm technology will be discussed. The loss was related to spacer bridging, blocking silicide formation and Lightly Doped Drain (LDD), source/drain implant. Soft Defect Localization (SDL) techniques [1], sub-micron Atomic Force Microscope (AFM) probing [2] and Time Resolved Emission (TRE) measurements were necessary to obtain an accurate understanding of the problem and the mechanism. Electrical results were compared to simulations. Modified test structures were implemented to monitor the process stability with respect to bridging failures.

Abstract Automotive ultrasonic parking sensors were analyzed using X- ray computed tomography (XCT or microtomography), in order to determine if there were internal failures generated on the soldering process between copper wires and piezoelectric ceramic on these sensors. This paper reports the use of X-ray radiography and computer image processing for the study of internal defects. By using X-ray tomography technique, pores, cracks, holes, solder balling, insufficient solder, lead related defects, device related defects, and solder bridging may be identified (1-2). When coupled with a real time radiographic detector and image processor, X-ray technology allows instantaneous radiographic imaging and semi-automatic or totally automatic inspection. Analysis was conducted on six produced test samples showing that the application of XCT as a method of quality control of specimens produced by electronic packaging offers a wide range of possibilities to detect defects within materials. There were determined that five sensors contain internal defects on the soldered joints, between the copper wire, and the piezo electric ceramic covered with silver paint, as shown on the computed tomography. Accuracy of XCT method strongly depends on the size of the samples analyzed, but the possibility of obtaining information in 3D nondestructively shows considerable advantages of XCT method over traditional metallographic cross-sectional analysis.