This paper offers an alternative solution in dealing with Focused Ion Beam (FIB) circuit edit debug of RF products that often required soldering the device onto a test board to enable sensitive RF characterization. Performing FIB circuit edit while the device is soldered on a test board not only eliminates signal degradation and inconsistency caused by a socket; but also, it allows for adding additional FIB edits on the same device. The conventional way of RF product debug of devices in a wire bond package was to characterize the device in a socket, perform the FIB circuit edit, encapsulate the cavity to protect the device from physical & thermal damage, solder the device onto the test board, and then perform post-FIB characterization. This is a very long, one-way process and needs multiple devices for design debug. For RF products in flip chip package, this approach was extremely difficult to almost impossible, because thermal stress of soldering device would significantly deform thinned die. All characterization had to be done with a socket, which often introduced changes of the same magnitude of the parameters of interest as well as repeatability issues. The purpose of this paper is to outline steps to allow for the RF FIB and characterization cycle to be done in a way to decrease throughput time and increase measurement accuracy. True characterization of highly sensitive RF circuit modifications is achieved through: soldering the device to the test board, performing sample preparation, preforming pre-FIB characterization, preforming FIB, and finally preforming post FIB characterization. Elimination of the need to solder a thinned device to a test board allows for the edit location to remain open enabling additional FIB edits to be performed on the same device. This eliminates redundant steps in the device sample preparation and enables quicker throughput times.

Multiple, independent, system level test failures that occurred around the same time were traced back to a short circuit on the same type of printed circuit board (PCB). The PCBs were removed from the application and sent to the authors' lab for analysis. This paper reviews the analysis techniques and results that led to the failure mechanism being identified. The discussion focuses on steps taken to exonerate the authors' lab and processes as possible sources of contamination. Additional investigation that leads to the conclusion that the issue is systemic is also covered. The paper then focuses on the containment effort as well as root cause identification at the manufacturers. It was concluded that the failure mechanism causing the short circuit in the failed PCB is due to ionic contamination trapped inside the PCB. The normal chemistry required to process the plated through holes contaminated the voids/fractures created by drilling process.

This paper is focused on the de-soldering process on VSON package which was mounted on FR4 substrate board after being subjected to environmental stress. Abnormalities were found at package level during Scanning Acoustic Microscopy (SAM) inspection which is considered to be one of the non-destructive failure analysis processes. Root cause finding involved the investigation of the de-soldering equipment which is suspected to be one of the culprits to contribute to the defect during de-soldering process.

This paper correlates the reseat failure rates of a PCI option card to the use of thin gold plating across the contact fingers. This failure mechanism results in increased contact resistance and is often misdiagnosed due to its intermittent failure mode. As many new manufactures appear in Asia, the push for global competitiveness to achieve high volume and reduced costs can result in insufficient plating finishes being applied to the contact fingers. Compounding this problem is the fact the many companies use multiple raw board suppliers to meet these volume requirements. Many times the end user of the option card is unaware of the wide variation in contact plating thickness that may be present from one raw board source to another. Intermittent failures are one of the most common defects experienced in high volume assembly. Unless properly diagnosed, these failures can be attributed to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting approach is followed, isolating the true root cause of the actual failure can be missed. The difficulty in identifying the reseat problem is compounded by the fact that the failures are often intermittent in nature. While reseating may temporarily achieve sufficient mating between the board’s contact fingers and the connector contacts, it provides no long term fix. These unnecessary reseats also reduce the long-term durability of already thin plating affecting customer satisfaction and warranty costs. In the paper, we will expand on the theory behind the XRF plating thickness testing, including: • System theory • Test calibration • Part orientation • Test measurement criteria Additional analysis of metallurgical cross-sectioning was performed to correlate the XRF test readings to the actual plated layers. The measurements were completed by use of a SEM (Scanning Electron Microscopy).

The continuing evolution of semiconductor packages to finer solder ball pitches, shrinking solder ball volume, and new solder materials, mandates the availability of methods to accurately assess solder joint reliability both at the component and at the board level. Many tests in use for this purpose cannot provide direct measurements of solder joint interfacial strength. This paper reports on the investigation of laser spallation for interfacial strength assessments and understanding of failure mechanisms on chip scale package (CSP) solder joints.

This paper is a review of propagating faults in printed circuit boards (PCBs) from the perspective of using the resulting burn and melted copper patterns to identify likely locations of fault initiation. Visual examination and x-ray imaging are the main techniques for examining PCB propagating faults. Once the likely fault initiation location has been identified, fault tree analysis can be used to determine the root cause for fault initiation. The paper discusses the mechanisms by which PCB propagating faults occur. The method of determining the likely area of initiation of the fault using visual examination of the PCB burn pattern, x-ray imaging, and the layout artwork for the PCB is discussed. The paper then goes on to discuss possible root-causes for the initiation of PCB propagating faults and some of their considerations.

Due to the development of semiconductor’s fabrication and design technologies, SOC (System-On-Chip) products have been improved to enable development of a one-chip solution, which integrates a high performance main processor and various IP blocks. With this successful technical development, it is necessary to have a high speed interface that is complicated between the main processor and each IP block, but this can be problematic when the interface must support system level functions even though each IP alone does not have any problem. Most semiconductor companies and those doing Failure Analysis (FA) have adopted Automatic Test Equipment (ATE) because of its efficiency, but in cases where faulty products are detected at the customer site with their specific set of operating functions, the FA engineers have difficulties because of the challenge to convert customer’s functions to ATE test functions. To get through such a difficult situation, this paper presents a novel FA solution, utilizing Laser Voltage Probing (LVP) and set evaluation software and hardware, instead of ATE. This new FA technique can reduce the time to solve a system level application problem, improve FA quality with accurate timing analysis (detecting a 400ps signal glitch) and meet customer satisfaction by improving product quality. Fundamentally, the results of this paper compensated for the weakness in design procedures of IP blocks or products by adopting an additional simulation tool, which should prevent the recurrence of same-type errors.

A PCB trace was repeatedly cracking in the same location. Visual inspection showed cracking there and at structurally similar locations, with solder mask missing from one side of the trace of interest. Fracture analysis suggested that these issues and etch pitting caused crack initiation, followed by fatigue failure that ultimately led to full fracture. A FIB section of a second failure reinforced the finding that the fundamental cracking mechanism was fatigue.

Board level semiconductor reliability testing (BLTT) is a crucial step in the product development life cycle of modern electronics. While the primary focus of semiconductor reliability historically has been to understand the robustness of the solder joint, there are other aspects of the semiconductor package which are also susceptible to failure after the product has been assembled. Despite its overwhelming importance, there is no one centralized resource outlining best practices for conducting BLRT across industries. Fortunately, industry standards do exist. Among them are outlines for conducting tests including temperature cycling, mechanical shock, humidity dwell among others. In this work we present a case study exploring some of the unique challenges and methods associated with conducting BLRT using mechanical shock testing. Namely, we discuss the practical challenges of conducting these tests in the presence of a constant noise source and performing die level failure analysis on components suffering from warpage while back side films (BSFs) are applied as a protective coating on the package.

This article outlines an optimal approach for board level CSP failure analysis, where the chip and printed circuit board are analyzed as a single unit to determine the root cause of the board level failures. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions, heating profiles or reflow, substrate warpage, and solder joint voids. This technique allows investigation of the above factors in a single sample preparation and readily arrive at the root cause solution in the minimum time. Results showed that package properties, the design of solder pads play the major role in determining how the fatigue behavior of solder joints will affect CSP component. Additional factors like nickel/gold and nickel palladium finishes were found to be more brittle and promote solder joint cracking.

In situ decapsulation of plastic devices can be used to avoid the removal or alteration of failure mechanisms caused by exposure to desoldering temperatures. This paper describes techniques to decapsulate devices mounted to a printed circuit board using materials that are readily available and easily customized to specific applications. The techniques are extended to the decapsulation of other packaging technologies, such as SBGA packages and chip-on-board assemblies. Finally, post decapsulation cleaning techniques that will not harm the printed circuit board material are presented.

The package to board interconnection shear strength (PBISS) test method yields an amalgamated measure of pad peel strength, solder/pad interfacial strength and bulk solder shear strength. This measure mirrors the reliability of the actual product better than any single component strength value. Using a novel fixture that ensures pure shear stresses on the package, the shear strengths of two different ball grid array packages with Sn62PbAg2 solder balls are characterized as a function of pad finish and board build-up layer type. The tests can be performed relatively quickly (< 15 minutes for an entire package on board) with good repeatability. Results indicate that the component shear test is sensitive to the variables studied and attractive as a candidate technique for quantifying solder joint quality and integrity on actual production samples for a variety of package types and sizes. Potential applications of this method are for materials/process/vendor evaluation during product development phase and as a production/supplier quality assessment tool in the factory. Key words: interconnection strength, shear test, area array package, solder joint, pad surface finish

This paper discusses the development of an electrical failure analysis workflow that uses a multifunction direct current tester (DCT) to map the location of defects associated with open and short circuits as well as leakage current. It explains how software and tooling were designed to accommodate a wide range of package types and sizes and how they were verified by testing. It also presents two case studies showing the accuracy of the defect mapping function for sockets with 0.8 and 1.0 mm ball pitch.

The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

Printed Circuit Boards (PCBs) are easy target for reverse engineering and counterfeiting attacks due to the distributed supply chain. The integrated circuits (ICs) authentication techniques such as Physically Unclonable Function (PUF) are not easily extendible to PCBs. In this paper, we analyze various sources of variations in PCB and qualitatively study the quality metrics that can be used to quantify the PCB PUFs. We propose several flavors of PCB PUFs by exploiting the manufacture process variations. We also propose a multi-stage arbiter PUF with exponential challenge response pairs. Our preliminary simulations revealed an average 50.4% inter-PCB hamming distance.

This paper describes the failure analysis methods used to characterize micro cracks that resulted in laser vias of printed circuit boards (PCBs) through case studies of destructive failure analysis. Defects such as cracks in laser vias of PCBs can cause open or low leakage failure mode of module due to improper cleaning during the PCB process, natural oxide films such as brown oxide, or physical forces by use. Therefore, it’s difficult to identify the causes of these phenomena unless proper analytical techniques are used. In this study, multiple analytical techniques are employed to characterize micro cracks in laser vias. The destructive analysis with cross section and ion milling process is used to detect and inspect an accurate micro crack phenomenon of laser via. The characterization analysis using TEM, EDX and SIMS equipment after separating laser vias from a PCB is used to analyze failure cause of micro crack in laser via. This paper will be concluded with a discussion about what physical analysis methods should be used to analyze the causes of micro cracks for laser vias of PCBs.

In this paper, we demonstrate a case for non-destructive detection of submicron wide via-crack in printed circuit boards (PCBs) by using in-situ thermal chamber 3D x-ray computed tomography. The defect location is verified by a PFA (Physical Failure Analysis), and good agreement was made. This fault isolation method is proposed as a possible solution for identifying submicron cracks in PCB substrates during challenging investigations.

Accelerated corrosion leading to system failure has been observed on printed circuit boards present in industrial environments that contain abnormal levels of reduced sulfur gasses, such as hydrogen sulfide (H2S) and elemental sulfur. The problem is compounded by the fact that elemental sulfur is regulated by OSHA as a nuisance dust, and is allowed in a human working environment at the parts per thousand levels. Anecdotal data shows clearly that elemental sulfur gas present at the parts per million level can cause computer systems to fail within 2 months of use. Newer technologies such as immersion silver plating are especially susceptible to this type of corrosion. With the rapid growth of organically coated copper (OCC) and immersion silver platings, the number of failures due to reduced sulfur gasses in the environment has risen substantially.

Failures in printed circuit boards account for a significant percentage of field returns in electronic products and systems. Conductive filament formation is an electrochemical process that requires the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. With the advent of lead-free initiatives, boards are being exposed to higher temperatures during lead-free solder processing. This can weaken the glass-fiber bonding, thus enhancing conductive filament formation. The effect of the inclusion of halogen-free flame retardants on conductive filament formation in printed circuit boards is also not completely understood. Previous studies, along with analysis and examinations conducted on printed circuit boards with failure sites that were due to conductive filament formation, have shown that the conductive path is typically formed along the delaminated fiber glass and epoxy resin interfaces. This paper is a result of a year-long study on the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style, and conductor spacing on times to failure due to conductive filament formation.

Superconducting Quantium Interferance Device (SQUID) microscopy uses detection of magnetic fields to image current paths within electronic devices and has been successful in non-destructively identifying the location of low leakage currents, even when the failure site was between a power and ground plane. This article presents a case study in which the customer was experiencing ignition of a 20-layer printed circuit board after approximately 1000 to 4000 operating hours in an indoor-controlled environment. High currents on the board resulted in extensive damage, effectively preventing initial identification of the failure site, failure mechanism, or root-cause. Based on a review of potential failure mechanisms, measurement of relevant parameters, and the results of SQUID microscopy, the process of electrochemical migration around or through the particles was determined to be the most likely root-cause of electrical shorting between power and ground.