It is generally accepted that the fault isolation of Vdd short and leakage can be globally addressed by liquid crystal analysis (LCA), photoemission analysis and/or laser stimulating techniques such as OBIRCH or TIVA. However, the hot spot detected by these techniques may be a secondary effect, rather than the exact physical defect location. Further electrical probing with knowledge of the circuit schematic and layout may still be required to pinpoint the exact physical defect location, so that a suitable physical analysis methodology can be chosen to identify the root cause of the failure. This paper has described a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques and finally the root cause of the Vdd leakage was identified.

This work presents the first application of a diagnosis driven approach for identifying systematic chain fail defects in order to reduce the time spent in failure analysis. The zonal analysis methodology that is applied separates devices into systematic and random populations of chain fails in order to prevent submitting random defects for failure analysis. Two silicon case studies are presented to validate the production worthiness of diagnosis driven yield analysis for chain fails. The defects uncovered in these case studies are very subtle and would be difficult to identify with any other methodology.

A new method of signature analysis is presented and explained. This method of signature analysis can be based on either experiential knowledge of failure analysis, observed data, or a combination of both. The method can also be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. The model is developed in the paper and an example is given for its use.

Reducing the cell size of DRAMs in 0.35 micron and follow-on technologies requires failure analysis techniques that can analyze single storage node trench capacitors on both test sites and actual product. A combination of electrical microprobing, probeless voltage contrast and physical delayering procedures, all based on focused- ion-beam (FIB) techniques, are described. Because of precise fail localization, high resolution scanning electron microscope (SEM) imaging enables the distinction between process defects and intrinsic breakdowns of node dielectric defects. Isolated storage cells can be electrically characterized by depositing small probe pads, using FIB for contact hole milling and probe-pad deposition. To localize trench capacitors with a leakage path to the surrounding substrate, the trenches are isolated by mechanical polishing and probeless voltage contrast in the FIB tool. Failing trench capacitors can be marked in the FIB tool. Physical isolation of leaking trench capacitors can be achieved by recessing the adjacent trench capacitors, with the FIB used for milling and a subsequent wet chemical removal added for the remaining substrate material. Alternatively, trench capacitors can be inspected from the backside when stabilized by a quartz deposition on top, followed by mechanical polishing from the side and a wet chemical etching of the remaining substrate material. In both cases, the dielectric of the node trench capacitors can be inspected by high resolution SEMs and the defect areas precisely analyzed.

This article explores the use of principal component analysis (PCA) and hierarchical clustering in the analysis of wafer level automatic test pattern generation (ATPG) failure data. The principle of commonality is extended by utilizing hierarchical clustering to collect die that are more similar to one another in their manner of failure than to others. Similarity is established by PCA of the patterns that the die in a wafer fail. Results demonstrated that PCA analysis and clustering are useful tools for dimensionality reduction and commonality analysis of wafer level ATPG data. The utility of PCA analysis and clustering in the extraction of die for physical failure analysis is also illustrated.

In the failure analysis of semiconductors, layout analysis to pick up suspect nets is getting to be a time consuming work due to finer wiring pitch and multi-layer structure. This article proposes a failure analysis navigation system (FA-Navigation System), which can make it easier to extract the nets passing through the signals detected by the hardware analysis tool, such as emission microscopes or OBIRCH analysis tools. It introduces the functions of the system and shows some case studies in actual failure analyses. The IDDQ fault diagnosis is especially useful for case studies. The result of the software diagnosis can be loaded in the analysis window of the FA-navigation system, and the system correlates the result to the nets extracted by the hardware analysis and displays coincident nets in a sorted manner to make the failure analysis easier.

Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.

Traditionally, many semiconductor companies have used SRAM memory to develop their process technologies. The job of the failure analyst is often to physically deprocess the sample and hope to find the defect with only the bit map location to guide them. The success rate has been better in the past when the size of these SRAM cell were bigger. With the technology shrinking every 2 years, the chance of finding physical defects has become less and less. Besides the shrinking SRAM cell geometries, the electrical failure signature for many of the failures is marginal (soft failure), presenting difficult challenges for failure analysis (FA). Physical analysis of these soft SRAM failures at the sub-100nm technologies is often non-visual without detailed isolation and electrical characterization. Therefore, additional techniques are needed to improve the successful FA on newer technologies. In this discussion, we will present the uses of both SCM/SSRM (scanning capacitance microscopy / scanning spreading resistance microscopy) analysis and nanoprobing technique for fail site isolation.

Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

Device failure analysis typically requires multiple systems for fault identification, preparation and analysis. In this paper we discuss the practicalities and limits of using a single FIBSEM system for a complete failure analysis workflow. The theoretical requirements of using a nanomanipulator for both lamella lift out and electrical testing are discussed and the current capabilities of windowless X-rays detectors for chemical analysis demonstrated. When the required resolution for failure analysis exceed the limits of a FIBSEM and TEM is required, the combination of the nanomanipulator and X-ray detector for advanced lift out and thickness controlled thinning techniques are demonstrated to prepare exceptional quality lamellae.

In this study, the challenges to transfer the microelectronics failure analysis techniques to the photovoltaic industry have been discussed. The main focus of this study was the PHEMOS as a tool with strong technological research capacity developed for microelectronics failure analysis, and OBIC (Optical Beam Induced Current) as a non-destructive technique for detecting and localizing various defects in semiconductor devices. This failure analysis tool was a high resolution optical infrared photon emission microscope used mainly in microelectronics for qualitative analysis and localization of semiconductor defects. Such failure analysis equipment was designed to meet requirements for modern microelectronic devices. Characterization of current photovoltaic device often requires quantitative analysis and should provide information about the electrical and material properties of the solar cell. Therefore, in addition to the demand for further data processing of the obtained results we had to study the corresponding operating regime of solar cells to allow for a correct interpretation of measurement results. In this paper, some of the related problems we faced during this study, e.g. large amount of data processing, the spatial misalignment of the images obtained as EL (Electroluminescence) and IR-LBIC (Infrared Light Beam Induced Current), the implemented laser wavelength, its profile and power density for IR-LBIC measurement. These topics have been discussed in detailed to facilitate a reliable transfer of these techniques from microelectronics to the photovoltaic world.

Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Moore”). This complex 3D geometry, with an abundance of opaque layers and interconnects, presents a great challenge for failure analysis (FA). Three-dimensional (3D) magnetic field imaging (MFI) has proven to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allows for submicron vertical resolution. 3D X-ray microscopy (XRM) enables 3D tomographic imaging of advanced IC packages without the need to destroy the device. This is because it employs both geometric and optical image magnifications to achieve high spatial resolution. In this paper, we propose a fully nondestructive, 3D-capable workflow for FA comprising 3D MFI and 3D XRM. We present an application of this novel workflow to 3D defect localization in a complex 2.5D device combining high bandwidth memory (HBM) devices and an application specific integrated circuit (ASIC) unit on a Si interposer with a signal pin electrical short failure.

New developments concerning lock-in phase detection and spectral analysis techniques applied to accessible IC signals are introduced in detail. These techniques combine the thermal laser stimulation (TLS) with the high sensitivity of lock-in to phase variation or the selectable frequency detection in spectrum analyzer. The difference to normal lock-in techniques utilizing pulsed lasers is exemplary pointed out. Moreover the applications to phase related soft-defects and to a design related jitter problem are shown. The power of such techniques for direct mapping a signal path is shown. Further benefits of lock-in phase methodology and spectral analysis technique applied to 65 nm and 90 nm technology is presented and illustrated using different case studies.

In this paper we will introduce novel methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non-destructive fault localization with efficient and accurate target preparation to get access for following microstructure diagnostics, forming a subsequent failure analysis workflow. The concept presented here involves the application of improved Lock-In Thermography (LIT), and three different innovative concepts of high rate Focused Ion Beam (FIB) techniques.

IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

A noninvasive backside probe of integrated circuits has been developed. This new probe can diagnose at-speed failures, stuck faults, and other defects. Because it is a highly parallel imaging technique, faults may be isolated which are difficult to locate by other methods. This optical technique has been named “PICA”, for picosecond imaging circuit analysis. PICA relies on the fact that an FET in a CMOS circuit emits a picosecond pulse of light each time the logic gate changes state. The source of this emission is explained. The PICA technique, which combines optical imaging of the emission with picosecond time-resolution, is described. Because of the imaging, time-resolved emission data is acquired for many transistors in parallel. The use of the emission for failure analysis and AC characterization of integrated circuits is demonstrated. Because the emission can be detected from either the front or back side of the chip, it can be used for both front and back side analysis.

Lock-In Thermography is an established nondestructive method for analyzing failures in microelectronic devices. In recent years, a major improvement made it possible to acquire time-resolved temperature responses of weak thermal spots, greatly enhancing defect localization in 3D stacked architectures. One limitation, however, is in the method used to determine defect depth, which is based on the numerical estimation of the delay between excitation and thermal response inferred from the value of the lock-in phase. In structures where the region between the origin of the defect and sample surface is partially or fully transparent to infrared signals, interference between radiated and conducted signal components largely falsifies the phase value on which the classical depth estimation relies. In the present study, blind source separation based on independent component analysis was successfully used to separate interfering signal components arising from direct thermal radiation and conduction, resulting in a precise estimation of the defect depth.

This presentation is an introduction to machine learning techniques and their application in semiconductor failure analysis. The presentation compares and contrasts supervised, unsupervised, and reinforcement learning methods, particularly for neural networks, and lays out the steps of a typical machine learning workflow, including the assessment of data quality. It also presents case studies in which machine learning is used to detect and classify circuit board defects and analyze scanning acoustic microscopy (SAM) data for blind source separation.

The trend to higher integration of electronic devices to include more functions into ever-smaller devices, such as mobile phones or tablet computers, drives the development of novel packaging technologies for semiconductor chips. One of the approaches to reduce packaging size and power consumption is to stack multiple silicon chips on top of each other. An alternative approach is the utilization of through-silicon vias (TSV) to connect multiple chips to each other. This paper provides a set of sample preparation and analysis techniques for the comprehensive analysis of TSVs in support of technology development and qualification. The toolset ranges from simple cross-section imaging of cleaved samples to the evaluation of wafer planarity at the end of the TSV process flow and to the more specific analysis of the stress field around TSVs. The results provide valuable insights for designers, integration engineers, and process engineers.

Anamnesis is known as an important method for pre-diagnosis in medical sciences. In device failure analysis (FA) it is not so far used, yet – especially with regard to system- and application-aspects. As a consequence, a lot of useless rootcause-related FA efforts are done on device level, while the root cause is on system level. Introduced by an illustrative case study, the benefit of a suitable anamnesis is shown as well as the way to do it – by posing the right questions before FA starts. Many FA efforts can be saved or optimized and frequently, a sound anamnesis already may lead towards the root-cause conclusion.