Accurately measuring parameter mismatch for analog MOSFETs, such as the threshold voltage (Vt) or W/L ratio, is often required in analog circuit failure analysis. The challenge in probing analog MOSFETs using atomic force probing (AFP) is contact resistance. Contact resistance between AFP tips and tungsten contacts can cause large error at high current. This paper discusses measurement error caused by contact resistance and the techniques to identify and reduce the contact resistance effect.

To reconstruct discrete device threshold characteristics at tungsten contact level with atomic force probe (AFP), specific care in making drive current measurements is essential. Kelvin probing as well as the proper placement of the AFP probes themselves is an absolute requirement for insuring precise measurements. For this paper, NFET and PFET test structures employing 3 micrometer gate widths are used to simulate a sense-amp device. The results obtained using normal pad-level probing on a conventional probe station with results from an AFP nanoprober with and without Kelvin sensing are compared. These measurements are also compared with the nominal or expected design rule values. Experimental results comparing AFP Kelvin measurements at contact level on the same MOSFET test structure versus measurement obtained conventionally at pad level underscores the importance and value of AFP Kelvin measurements.

Two cases of high temperature failure analyses are presented. In both cases an on-chip “heater” – power MOSFET was used to achieve high temperature for both global fault isolation and block/transistor level nodal analysis. The “heater” provides a quick and effective way of changing the device temperature without significantly modifying the bench setup. In both cases, the results show improved probability of successfully isolating the fail site, by performing OBIRCH analysis and nodal analysis.

The shift in power conversion and power management applications to thick copper clip technologies and thinner silicon dies enable high-current connections (overcoming limitations of common wire bond) and enhance the heat dissipation properties of System-in-Package solutions. Powerstage innovation integrates enhanced gate drivers with two MOSFETs combining vertical current flow with a lateral power MOSFET. It provides a low on-resistance and requires an extremely low gate charge with industry-standard package outlines - a combination not previously possible with existing silicon platforms. These advancements in both silicon and 3D Multi-Chip- Module packaging complexity present multifaceted challenges to the failure analyst. The various height levels and assembly interfaces can be difficult to deprocess while maintaining all the critical evidence. Further complicating failure isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete power MOSFET perspective amidst the competing forces of the system-to-board-level failure analysis. It underlines the requirement for diligent analysis at every step and the importance as an analyst to contest the conflicting assumptions of challenging customers. Automatic Test Equipment (ATE) data-logs reported elevated power MOSFET leakage. Initial assumptions believed a MOSFET silicon process issue existed. Through methodical anamnesis and systematic analysis, the true failure was correctly isolated and the power MOSFET vindicated. The authors emphasize the importance of investigating all available evidence, from a macro to micro 3D package perspective, to achieve the bona fide path forward and true root cause.

We analyzed the gain error issue and non-linearity issue of a precise Analog-to-Digital Converter (ADC) and found the root cause to be Random Telegraph Signal (RTS) noise in bipolar devices. The RTS noise produced nearly 1mV abrupt changes in a band-gap reference voltage, and affected ADC and other circuits where the reference voltage was used. We developed a new measurement method enabling us to detect RTS noise in bipolar with higher signal-to-noise ratio than traditional methods. We also developed an algorithm to extract RTS occurrence frequency and average magnitude. The RTS characterization capability has helped us invent a new bipolar structure and develop new processes to minimize RTS noise.

Random Telegraph Signal (RTS), also described as popcorn noise in semiconductor analog circuits occurs when there is a sudden step in threshold voltage for a MOSFET or sudden step in base current for a bipolar transistor. The causes of popcorn noise can be process-related in semiconductor manufacturing. This paper presents a nanoprobe analysis methodology that was able to detect popcorn noise issues in discrete transistors causing analog circuit failure. The results presented for two different devices obtained similar results proving that the analysis methodology is viable for detecting popcorn noise issues in semiconductor MOSFET transistors. From a failure analysis perspective, the purpose of this paper is to provide the ability and a methodology to detect a signal that differentiates a failing transistor (popcorn noise) from a non-failing transistor (no popcorn noise). In this regard, the ability to obtain these results was not only unexpected but also very successful.

This paper describes a novel flow using analog simulations for the failure analysis of digital, analog, and mixed signal devices. Although cell level diagnosis tools are available in the industry, it presents a solution through analog intra-cell simulation particularly advantageous when multiple defects give the same fault result at cell level. Details of case studies such as the one analog intracell simulation on digital device and the analog laser voltage probing are covered. The aim of the simulation solution proposed is to support the failure analyst to interpret emission images on analog devices. The presented analog simulation flow consists of computing the current (or current density) in MOS and bipolar transistors and simulating the internal waveforms in digital or analog cells. It enables failure analysts to interpret light emission and laser voltage probing results obtained on a physical device in a fast and efficient way.

Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

Based on the understanding of laser based techniques’ physics theory and the topology/structure of analog circuit systems with feedback loops, the propagation of laser induced voltage/current alteration inside the analog IC is evaluated. A setup connection scheme is proposed to monitor this voltage/current alteration to achieve a better success rate in finding the fail site or defect. Finally, a case of successful isolation of a high resistance via on an analog device is presented.

Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

In this paper, the differential and lockin imaging techniques of Dynamic Photon Emission (DPE) were developed by using highly sensitive near-infrared InGaAs camera in time integrated mode. At first, the setup and method for differential imaging of DPE (DI-DPE) are introduced. The unique debug and pinpointing capability of fails of DI-PEM is discussed in combination with two case studies. Based on DI-DPE, the setup and method for Lockin imaging of DPE (LI-DPE) are then developed for such cases where the correlated DPE is enhanced in strong photon emission background. The correlation in LI-DPE can separate the emission spots from different power domains.

We compare different dc current-based integrated capacitance measurement techniques in terms of their applicability to modern CMOS technologies. The winning approach uses quadrature detection to measure mutual Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) capacitances. We describe our implementation of this approach, Quadrature-clocked Voltage-dependent Capacitance Measurements (QVCM), and its application to 45 nm node BEOL: wire capacitance variability measurements for analog design, and capacitive test structure to measure the effect of metal pattern density on Chemical-Mechanical Polishing (CMP) and Reactive Ion Etching (RIE).

As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].

Possible reliability failure mechanisms on mixed-signal IC are reviewed and categorized. Based on the nature of reliability and low DPPM failures on mixed signal IC, an analysis flow is proposed including identification of individual failure mechanisms, extraction of the systematic problems, and implementation of corrective actions. Finally, a case of successful isolation of a specific defect without common electrical signature on mixed-signal devices is presented.

During the last years, laser reflectance modulation measurements (i.e. LVI, CW-SIP etc.) have become indispensable tools for the analysis of logic circuits at frequencies in the megahertz range. In this paper we present a method to extend the usefulness of these methods to mixedsignal circuits driven at ultra-low frequencies in the kilohertz range. We show that by toggling the main power supply, information of the electric behavior can be easily obtained from analog structures, removing the need for tester-based stimulation. This method proved especially useful for the debugging of chip startup failures. We demonstrate this with two case studies. In a first case, a defect in the analog part shut down the digital part of the chip. This prevented the use of debugging methods such as the read-out of error registers or the use of scan chains. Conventional methods like photon emission microscopy and thermal laser stimulation were also not successful at finding the problem. However, laser-voltage imaging (LVI) of the analog circuit at key locations while toggling the chip power supply in the kilohertz range led us to the failing net. In a second case on a different product, we similarly identified a failing capacitor in the error logic by modulating the chip enable pin in the kilohertz range.

The lock-in phase mapping technique with modulated reflectance is introduced for the first time. With its help, the modulated reflectance mechanisms using thermal laser in operating FETs, particularly in the pinch off region, are clarified. The free carrier absorption mechanism dominates at a high modulation frequency, while thermo-reflectance mechanisms at a low modulation frequency. In the pinch-off region, thermo-reflectance mechanism cannot be neglected due to extremely low free carrier concentration. The modulated reflectance signal was unexpectedly observed at passive poly/oxide/poly capacitance. The advantages of lockin phase mapping in dynamically operating mixed-signal IC devices are shown in several case studies.

As semiconductor technology continues to advance to smaller dimensions and more complex circuit designs, it is becoming more challenging to locate the resistive short directly between two metal lines (signals) due to a metal bridge defect. Especially these two metal lines are very long and relevant to many functional modules. After studying the failed circuit model, we found there should be a tiny leakage between one of the bridged signals and one of common power signals (such as VDD and GND) on a failed IC compared with the reference one, if there is a metal bridge defect between these two bridged signals. The tiny leakage between one of the bridged signals and one of power signals is an indirect leakage that is a mapping of the direct resistive short between these two bridged signals. The metal bridge defect could be pinpointed with the tiny leakage between one of the bridged signals and one of power signals by Lock-in IR-OBIRCH. It is an easier and faster way to locate the metal bridge defects. In this paper, the basic and simple circuit model with a metal bridge defect will be presented and two cases will be studied to demonstrate how to localize a metal bridge defect by the tiny leakage between one of the bridged signals and one of power signals.

Performance degradation due to fatigue accumulation from the repetitive switching of high load current is critical to understanding robust power MOSFET product design. In this paper, we present a novel high-current-temperature (HCT) characterization system used to investigate real world powercycling failure mechanisms. The effects of electric current Joule heating, non-uniform temperature distribution and performance deterioration of discrete power devices are discussed. Thermal fatigue of solder joints and thick aluminum wire bonding are common weak spots with regard to power-cycling capability. We report performance failure mechanisms and discuss the superposition of contributing factors in defining root cause. Results discuss various package influences as part of a robust power MOSFET development process.

Modern semiconductor devices are continuing to be scaled down and the complexity of the processes involved in producing the devices keeps increasing, in conjunction with this, sample preparation and analysis are increasingly important for accurately determining the sources of defects and failure mechanisms in terms of process integration. This paper discusses ways to characterize integration-driven defects using deprocessing techniques and cross-section imaging to obtain 3-D views of such defects. As an example a single-via test structure is evaluated. The article focuses on the techniques used to deprocess the single-via structure using a combination of RIE, FIB, and wet etching to expose the single via while maintaining the integrity of the structure. The resulting 3-D view of the structure and associated defect allowed for improved understanding of the defect and its origin. This understanding enabled process optimization to minimize such defect formation.

Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.