1-20 of 81 Search Results for

NAND

Follow your search
Access your saved searches in your account

Would you like to receive an alert when new items match your search?
Close Modal
Sort by
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 256-259, November 5–9, 2017,
... by reducing striations and damages during FIB milling. Generally, the effect of air gaps between wordlines or between metal lines, as well as some unexpected defect voids can be eliminated in most cases if this ideal method is applied. air gaps carbon deposition focused ion beam milling NAND flash...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 227-231, November 10–14, 2019,
...Abstract Abstract The development of vertical 3D NAND technology over the past 5 years has been accelerated by the parallel development of metrology techniques capable of characterizing these device stacks. Current trends point toward a continuous scaling of dimensions along the z-axis...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 42-45, November 15–19, 2020,
...Abstract Abstract In this work, two analysis methods for word line (WL) defect localization in NAND flash memory array are presented. One is to use the Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH) to analyze the device through backside, which has no risk...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 20-22, October 31–November 4, 2021,
...Abstract Abstract In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) are tuned in order to optimize performance and validity. In this paper, we propose a machine learning optimization technique that uses deep learning (DL) and genetic algorithms (GA...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 141-145, October 31–November 4, 2021,
...Abstract Abstract This paper evaluates the use of plasma etching for preparing TEM specimens to analyze high aspect ratio 3D NAND integrated circuits. By controlling plasma etching parameters, a relatively high material removal rate could be obtained. Moreover, through the control of etch time...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 306-308, October 31–November 4, 2021,
...Abstract Abstract This paper presents a novel approach for detecting channel hole bending (ChB) defects in vertical NAND flash memory. Such defects are the result of etching process inconsistencies and contribute to data loss and device failure by inducing leakage current between adjacent...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 313-315, October 31–November 4, 2021,
...Abstract Abstract This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells. Despite the high aspect ratio...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 342-346, October 31–November 4, 2021,
...Abstract Abstract This paper presents a method for determining positional variation and offsets in high aspect ratio etches used in the production of 3D NAND devices. The method uses a 3D fiducial as a positional reference in the field-of-view, which not only allows for high precision tracking...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 347-351, October 31–November 4, 2021,
...Abstract Abstract This paper discusses the development of an automated cell layer counting process for preparing 3D NAND flash memory samples for TEM analysis. In an initial proof-of-concept, several line markings were inscribed on the test device in evenly spaced intervals in order to evaluate...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 406-409, October 31–November 4, 2021,
... automatically in the course of NAND flash memory manufacturing. Our proposed technique consists of the two steps: pre-processing and hybrid clustering. The pre-processing step based on process primitives efficiently eliminates noisy data. Then, the hybrid clustering step dramatically reduces the total amount...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 209-214, November 10–14, 2019,
...-NAND device where process induced variation in the high aspect ratio vertical memory channels is measured and to a double stack 3D-NAND architecture, which is comprised of two 32-layer stacks where eccentricity of the pillars was evaluated for layers in both upper and lower stacks. In addition...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 332-338, November 2–6, 2008,
... value IC defined as 1. VOL is the maximum output value IC: 0. VOH is the minimum output value IC understood as 1. The device examined to illustrate the methodology is a simple Quad 2-Input NAND Gate. The methodology aims at defining how far operating parameter margins can be extended. For a NAND gate...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 35-41, November 1–5, 2015,
... that captured the output and is compared to what is expected by the test. A simple circuit like a 2-input NAND gate will need at least 4 patterns (combinations of 0 and 1 on either input) to test its functionality completely. Based on the test results of an exhaustive pattern list, a scan diagnostics tool...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 520-526, November 6–10, 2016,
... the phenomenon of the buildup voltage on the inverter s floating input resulting in transistor saturation and induced photon emission. Table 1. Summary of the PEM results of 2-input NAND and 3- input NOR with single floating input and elevated VDD Next, the floating input scenarios on standard combinational...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 133-140, November 15–19, 2020,
... and exceptional specimen thickness. Two advanced semiconductor devices 20 nm NAND (solid state drive, IM Flash Technologies) and 7 nm finFET (A12 Bionic chip, TSMC) were prepared using the method described above. Bulk sample preparation by Ar BIB milling and conventional FIB lift-out specimen preparation Top...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 156-160, October 28–November 1, 2018,
... should be on one net called net 278, which is the connection net from one NAND to one ADDER in a multiplier block. The approximate structure around the diagnostic result is shown in Fig.4. Figure 4: Approximate block structure According to the background information, EOFM and EMMI (Emission Microscopy...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 592-596, November 5–9, 2017,
..., as well as a precise and controlled delayering process [7]. Experiment The experiment was performed on two commercially available devices: 3D vertical stack memory (Samsung 3D V-NAND) and a solid-state drive (SSD) containing air gap architecture [Intel]. The devices were chosen because the elaborate...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 613-615, November 14–18, 2004,
... drivers are side by side. Each driver consists of a NAND gate on the left and a NOR gate on the right. The nFETs of these gates are evident below centre and the pFETs appear as the faint luminescences above. Copyright © 2004 ASM International® All rights reserved. www.asminternational.org ISTFA 2004...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 68-75, November 6–10, 2016,
... analysis on NAND circuits using 1319 nm as probing laser on tools from different supplier vs case a), b) and c). Figure 11 below shows a two input NAND circuit probed with 1319nm laser and the circuit diagram as well as the CAD layout. Figure 11, NAND circuit from a 14 nm MPU. Left: waveforms using 1319 nm...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 295-301, November 10–14, 2019,
.... www.asminternational.org 295 DOI: 10.31399/asm.cp.istfa2019p0295 Discussion Bulk cross-section sample preparation A NAND solid state drive (SSD) device [Intel] with gate air- gap features was depackaged and from it a cross-section specimen was created by cleaving and subsequent ion milling. Ion milling was performed using...