Lock-in thermography (LIT) has been successfully applied in different excitation and analysis modes including classical LIT, analysis of the time-resolved temperature response (TRTR) upon square wave excitation and TRTR analysis in combination with arbitrary waveform stimulation. The results obtained by both classical square wave- and arbitrary waveform stimulation showed excellent agreement. Phase and amplitudes values extracted by classical LIT analysis and by Fourier analysis of the time resolved temperature response also coincided, as expected from the underlying system theory. In addition to a conceptual test vehicle represented by a point-shaped thermal source, two semiconductor packages with actual defects were studied and the obtained results are presented herein. The benefit of multi-parametric imaging for identification of a defect’s lateral position in the presence of multiple hot spots was also demonstrated. For axial localization, the phase shift values have been extracted as a function of frequency [4]. For comparative validation, LIT analyses were conducted in both square wave and arbitrary waveform excitation using custom designed and sample-specific stimulation signals. In both cases result verification was performed employing X-ray, scanning electron microscopy (SEM) and energy dispersive x-ray (EDX) as complementary techniques.

Lock-in thermography and magnetic current imaging are emerging as the two image-based fault isolation methods most capable of meeting the challenges of short and open defect localization in thick, opaque assemblies. Such devices are rapidly becoming prevalent as 3D integration begins to ramp up production. This paper expands on previously published work with a qualitative comparison of the techniques on single chip and stacked die packages with known designed-in or FIB created defects.

Lock-in thermography based on an infrared camera has proven to be a useful tool for failure analysis of integrated circuits (ICs). This article discusses four novel technical developments of lock-in thermography. These developments are blackening the IC surface with colloidal bismuth, the synchronous undersampling technique allowing the use of higher lock-in frequencies, displaying the 0deg/-90deg signal as a novel high resolution emissivity corrected image type, and removing the thermal blurring effect by mathematically deconvoluting the 0deg/-90deg; signal. The effect of these techniques is demonstrated by using a regularly working operational amplifier (pA 741) and a damaged capacitor as test devices. It is shown that blackening the IC surface improves the detection sensitivity in metallized regions by up to a factor of 10, whereas the other methods allow improvement of the effective spatial resolution. The article also discusses which of the spatial resolution improvement techniques is most appropriate in different situations.

Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator.

The advent of lock-in thermal imaging application on semiconductor failure analysis added capability to localize failures through thermal activity (emission) of the die. When coupled with creative electrical set-up and material preparations, lock-in thermography (LIT) [1, 2] application gives more possibility in exploring the failure of the device using low power settings. This gives higher probability of preserving the defect which leads to a more conclusive root cause determination.

Lock-In Thermography is an established nondestructive method for analyzing failures in microelectronic devices. In recent years, a major improvement made it possible to acquire time-resolved temperature responses of weak thermal spots, greatly enhancing defect localization in 3D stacked architectures. One limitation, however, is in the method used to determine defect depth, which is based on the numerical estimation of the delay between excitation and thermal response inferred from the value of the lock-in phase. In structures where the region between the origin of the defect and sample surface is partially or fully transparent to infrared signals, interference between radiated and conducted signal components largely falsifies the phase value on which the classical depth estimation relies. In the present study, blind source separation based on independent component analysis was successfully used to separate interfering signal components arising from direct thermal radiation and conduction, resulting in a precise estimation of the defect depth.

With the growing variety, complexity and market share of 3D packaged devices, package level FA is also facing new challenges and higher demand. This paper presents Lock-In Thermography (LIT) for fully non-destructive 3D defect localization of electrical active defects. After a short introduction of the basic LIT theory, two slightly different approaches of LIT based 3D localization will be discussed based on two case studies. The first approach relies on package internal reference heat sources (e.g. I/O-diodes) on different die levels. The second approach makes use of calibrated 3D simulation software to yield the differentiation between die levels in 8 die µSD technology.

The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (<150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.

The electronic properties of solar cells, particularly multicrystalline silicon-based ones, are distributed spatially inhomogeneous, where regions of poor quality may degrade the performance of the whole cell. These inhomogeneities mostly affect the dark current-voltage (I-V) characteristic, which decisively affects the efficiency. Since the grid distributes the local voltage homogeneously across the cell and leads to lateral balancing currents, local light beam-induced current methods alone cannot be used to image local cell efficiency parameters. Lock-in thermography (LIT) is the method of choice for imaging inhomogeneities of the dark I-V characteristic. This contribution introduces a novel method for evaluating a number of LIT images taken at different applied biases. By pixel-wise fitting the data to a two diode model and taking into account local series resistance and short circuit current density data, realistically simulated images of the other cell efficiency parameters (open circuit voltage, fill factor, and efficiency) are obtained. Moreover, simulated local and global dark and illuminated I-V characteristics are obtained, also for various illumination intensities. These local efficiency data are expectation values, which would hold if a homogeneous solar cell had the properties of the selected region of the inhomogeneous cell. Alternatively, also local efficiency data holding for the cell working at its own maximum power point may be generated. The amount of degradation of different cell efficiency parameters in some local defect positions is an indication how dangerous these defects are for degrading this parameter of the whole cell. The method allows to virtually 'cut out' certain defects for checking their influence on the global characteristics. Thus, by applying this method, a detailed local efficiency analysis of locally inhomogeneous solar cells is possible. It can be reliably predicted how a cell would improve if certain defects could be avoided. This method is implemented in a software code, which is available.

This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

We developed the non-destructive failure analysis method that is combination of Lock-in thermography (LIT) and high resolution 3D oblique CT. It made possible to complete the total analysis efficiently, because we can distinguish the type of failure by this non-destructive method.

Lock-in Thermography in combination with spectral phase shift analysis provides a capability for non-destructive 3D localization of resistive defects in packaged and multi stacked die devices. In this paper a novel post processing approach will be presented allowing a significant reduction of measurement time by factor >5 in comparison to the standard measurement routine. The feasibility of the approach is demonstrated on a specific test specimen made from ideal homogenous and opaque material and furthermore on a packaged hall sensor device. Within the case studies the results of multiple single LIT measurements were compared with the new multi harmonics data analysis approach.

In this paper new thermographic techniques with significant improved temperature and/or spatial resolution are presented and compared with existing techniques. In infrared (IR) lock-in thermography heat sources in an electronic device are periodically activated electrically, and the surface is imaged by a free-running IR camera. By computer processing and averaging the images over a certain acquisition time, a surface temperature modulation below 100 µK can be resolved. Moreover, the effective spatial resolution is considerably improved compared to stead-state thermal imaging techniques, since the lateral heat diffusion is suppressed in this a.c. technique. However, a serious limitation is that the spatial resolution is limited to about 5 microns due to the IR wavelength range of 3 -5 µm used by the IR camera. Nevertheless, we demonstrate that lock-in thermography reliably allows the detection of defects in ICs if their power exceeds some 10 µW. The imaging can be performed also through the silicon substrate from the backside of the chip. Also the well-known fluorescent microthermal imaging (FMI) technique can be be used in lock-in mode, leading to a temperature resolution in the mK range, but a spatial resolution below 1 micron.

The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.

The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.

It has been shown that microscopic Lock-in-Thermography (LiT) can be used for localization of electrical active defects like shorts and resistive opens in integrated circuits. This paper deals with the application of LiT for non-destructive failure analysis of fully packaged single and multi chip devices. In this case inner hot spots generated by the electrical defects typically can not be imaged directly because the mold compound or adhesives above are not IR transparent. Inner hot spots can only be detected by measuring the corresponded temperature field at the device surface. By means of failed and test devices will be shown, that LiT is sensitive enough to measure such temperature fields. In addition to the lateral localization of inner hot spots its depth can also be determined by measuring the phase shift between the electrical excitation and the thermal response at the device surface. Furthermore, the influence of the lock-in-frequency and mold compound thickness to lateral resolution and signal to noise ratio will be discussed. Using real failed single chip and stacked die devices two analysis flows were demonstrated to locate inner defects.

This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

In this paper the application of solid immersion lenses (SIL) in combination with Lock-in Thermography will be demonstrated for backside defect localization. The paper will give an introduction into Lock-in Thermography technique and presents a new developed easy-to-use holding system to adapt SIL for high resolution thermal imaging. It will be shown that defect localization can be applied from the backside of the chip up to a silicon thickness of 250µm using the same SIL. The relationship between the bulk silicon thickness and the resulting optical parameters was investigated.

It was already demonstrated, that the method of Lock-in Thermography (LIT) enables 3D localization of thermal active defects, e.g. electrical shorts and resistive opens, on die level and within fully packaged single and multichip devices [1,2]. The depth of a defect can be derived from phase shift measurements of the defective compared to a reference device For a general approach of this method, thermal modeling is used and verified by experimental data to investigate the internal heat propagation under periodic stimulation in correlation to the LIT measuring process. [3]. A basic requirement for the successful application of the method is a precise and reproducible measurement of both the thermal material properties of each material layer and the phase shift between the internal heat excitation and thermal response measured by LIT. Significant influences from the material and measurement setup to the detected phase shift have to be identified and taken into account. However, to identify and distinguish the relevant influences measurements with defined internal heat sources are necessary which are presented in this paper. First, the relationship between geometrical thickness of a material layer and the resulting thermal parameters for both homogeneous and heterogeneous materials are measured and discussed. A new measurement setup generating a defined point heat source will be presented to calibrate the LIT system for quantitative phase shift measurements and to determine the phase shift to thickness parameters of single material layers. In addition the variation of the phase shift caused by the defect geometry and the defect environment will be investigated. Finally, a case study is presented comparing the experimental results to the obtained results from a real stacked die device.

The relative effectiveness of lock-in thermography and magnetic current imaging for identifying defects in packaged ICs was studied by directly comparing results on the same three devices. One known (in-lab fabricated) and two unknown (field return) defects were studied in organic flip-chip and wirebond configurations. Both methods succeeded in identifying the defective area but significant differences were observed in the qualitative nature of the signals, XY localization resolution, and sensitivity. Depth estimates were obtained where possible which aided in localization.