Search Results for ISTFA Conference

The papers in this volume are based on presentations accepted for the 46th International Symposium for Testing and Failure Analysis, ISTFA 2020, that was scheduled to be held from November 15 to 19, 2020, in Pasadena, California, USA. The conference was cancelled due to the coronavirus (COVID-19) pandemic.

This paper discusses the application of the RF-LIT technique to a variety of use cases. The technique itself was introduced during last year’s ISTFA 2023 conference. The present work aims to showcase its suitability for the analysis of polyline cracks and packaging related fails such as via opens in RDL as well as cracks in solder joints. Further, a model is constructed explaining why RF-LIT can work and where the frequency dependence comes from.

Listings of the EDFAS 2023 Board of Directors and the ISTFA 2023 Organizing Committee and Session Chairs.

Listings of the EDFAS 2023 Board of Directors and the ISTFA 2023 Organizing Committee and Session Chairs.

Listings of the EDFAS 2024 Board of Directors and the ISTFA 2024 Organizing Committee and Session Chairs.

Listings of the EDFAS 2024 Board of Directors and the ISTFA 2024 Organizing Committee and Session Chairs.

Listings of the EDFAS 2022 Board of Directors and the ISTFA 2022 Organizing Committee and Session Chairs.

Cross sections of large Through Silicon Vias (TSV) and solder bumps are often prepared using the Focused Ion Beam (FIB). The high current Xe plasma ion source allows fast and precise target preparation of TSV with small diameter. Solder bumps can be accessed due to the high milling rate too. However, the high current milling by plasma FIB causes the worsening of the milled surface quality. An optimized FIB scanning strategy accompanied with the novel rocking stage for the sample tilting during the milling has been developed for the plasma FIB. Whole milling process is observed by the Scanning Electron Microscopy (SEM). Time to prepare a cross section is accelerated and the excellent quality is suitable for subsequent failure analysis. Also important is proper sample cleaving before FIB milling. Using an accurate method to cleave the sample prior to FIB preparation further reduces the overall sample preparation time. The high quality cross sections prepared using this new method are ready not only for SEM but also for EDX and EBSD analysis, either 2D or 3D, when combined with FIB slicing. Broadening the analysis to these techniques increases the obtainable information, allowing the arrangement of materials and their crystalline structure to be studied in a detail.

With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of intermetal layer in nanoscale devices is discussed. The proposed chemical etch and backside chemical etch PFA techniques have the advantages of sample preparation evenness and efficiency compared to conventional PFA. This technique also offers a better understanding of the failure mechanism and is easier to execute in identifying the vertical short issue.

As feature sizes are shrinking beyond 130nm, fresh subsets of failures are coming to light. Multiple site defect analysis with adjacent block comparisons and multiple site comparative nanoprobing have become mandatory for these extraordinary and non-visible defects. There are instances where inspection or analysis will be required at multiple sites over a wide area on a sample. Traditional mechanical deprocessing techniques do not allow us to maintain planarity over a relatively large area, typically tens of microns. This article presents a 'masking technique' that addresses the issue of 'adjusting' the level at several local sites on a microchip. This technique can be utilized at all deprocessing levels of defect analysis and comparative circuit analysis and is time, tools, and labor efficient. Additionally, it enables multiple site nanoprobing, a preferred and essential tool for electrical validation of non-visible failures at technologies 90nm and beyond.

Advanced node semiconductor reverse engineering has always demanded cutting-edge techniques to cleanly extract the key structural information from the integrated circuit (IC) design. Core circuit edit technologies such as taking a backside wafer approach, employing scanning focused ion beam (FIB) recipes, optimized chemical delivery, and endpoint technology based on ultraviolet (UV) photon spectroscopy can play an important role in success. Once delayered, the IC's structural layers can be subjected to high-resolution scanning electron microscope (SEM) imaging. A new tool has been developed that incorporates these capabilities for dedicated IC delayering. These capabilities allow for the visualization of individual layers, transistors, interconnects, and other critical elements at nanometer-scale resolution, unveiling valuable insights into the IC's design and functionality.

The task of differentiating precisely between EOS and ESD failures continues to be a challenging one for Failure Analysis Engineers. Electrical OverStress (EOS) failures on the die surface (burnt/fused metallization) of an IC can be characterized mainly by the discoloration at the site of the failures. This is in direct contrast to the lack of discoloration characteristic of ESD failures, which occur almost exclusively below the die surface (oxide and junction failures). To aid in this distinction, this paper attempts to present the underlying physics behind the discoloration produced in the EOS failures. For the EOS failures, the metal fuses due to the longer pulse widths (sec to msec), while for the ESD failures, the silicon melts because of the shorter pulse widths (< < 500 nsec) and higher energy. After EOS, the aluminum surface becomes dark and rough and the oxide in the surrounding area becomes deformed and distorted, resulting in the discoloration observed in the light microscope. This EOS discoloration could be due to one or more of the following: 1) morphological and structural changes at the metal/glass interface and the glass itself; 2) changes in the thickness and scattering behavior of the glass and metal in the failed areas.

Presentation slides for the ISTFA 2024 Tutorial session “TEM Sample Preparation for Electron Microscopy Characterization and Failure Analysis of Advanced Semiconductor Devices.”

Advanced RF IC’s incorporate numerous components along with the CMOS circuitry. One component is a metal-insulator-metal (MIM) capacitor. Test capacitors have been stressed using accelerated voltage and temperature conditions to assess the long-term reliability. This paper describes a methodology for evaluating the MIM capacitors that have failed during reliability testing. IR microthermography was developed to detect leakage locations in areas that are not visible to optical inspection or standard emission microscopes. These areas were deprocessed to correlate the IR emission and physical defect locations. This information is utilized to understand the failures and improve the reliability.

Challenges in sample preparation for semiconductor failure analysis are always increasing as more complex material and smaller dimensions are required to meet the needs of the semiconductor industry. These changes require the constant need for more refined procedures in all areas of sample preparation, including mechanical polish. This paper presents a newly modified technique which increases the planarity at the critical edge of the sample and results in a larger planar region of interest. The novel method combines both a blocked reactive ion etching and a standard planar polish. It has proven to be a successful delayering technique and helpful in facilitating further analysis. This method has been verified on dies, wafer pieces, and dies thinned and attached to blank silicon for support. It is useful for increasing overall planarity and particularly helpful for the extreme edge.

As device packages become smaller, the job of failure analysts becomes more difficult. Other complex configurations such as Small Outline Packages (SOP) pose unique problems. The difficulty of removing the encapsulant while preserving the integrity of the die, bond pads, bond wires and lead frame interconnects on a small outline package pose a serious problem. A new sample preparation technique is offered in order to expose the front side and backside of the die. This technique dramatically reduced the risk of damage and ensures the functionality of the device after decapsulation.

In the last several years emission microscopy has become an essential tool for failure analysis, specifically for VLSI devices. This paper describes various die related failure mechanisms in CMOS ASIC devices which were detected by emission microscopy. The failure analysis results discussed in this paper are primarily of the devices which were analyzed over the period of the last three years, 1994 - 1996. These devices were from a broad spectrum of final test failures, qualification and reliability test failures, special evaluation failures, testing and assembly failures at customer sites, and end user field failures. In addition to the failure mechanism statistic scanning electron micrographic illustrations of some of the failure mechanisms and associated damage are presented in this paper. The data presented in this paper clearly show the effectiveness of photon emission microscopy. The value of emission microscopy really lies in quick detection of failure locations on the die which failed functionally or due to excessive static IOD, functional IOD, or input/output leakage currents. It has certainly impacted tum around time of the analysis as significant reduction in analysis time has been achieved. In some cases same day turn around was possible.