Abstract Although the physical limits of CMOS scaling should have been reached years ago, the process is still ongoing due to continuous improvements in material quality and analytical techniques. This paper describes one such technique, electron channeling contrast imaging (ECCI), explaining how it is used to analyze nanoscale features and defects. ECCI allows for fast, nondestructive characterization and has the potential for extremely low detection limits. The detection of low-level defects requires measurements over large areas (usually with the help of automation) to obtain statistically relevant data. For example, automated ECCI mapping routines have been shown to quantify crystal defect densities as low as 1 x 10 5 cm -2 in epitaxially grown Si 0.75 Ge 0.25 . The paper presents various methods to reduce measurement time without compromising sensitivity. It also explains how the mapping routine can be optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers.

Abstract As the semiconductor industry continues to push the boundaries of Moore’s law, new device structures and materials are being introduced to increase device speed and lower power consumption. This work uses InGaAs as representative samples to investigate the capability of conductive AFM to image and characterize electrical defects in thin films. As the AFM is a non-destructive technique, the defects may be re-located by complimentary reference metrology techniques. Once the capability of defect detection and characterization of AFM is demonstrated with respect to the reference metrology techniques, conductive AFM is used to characterize the defect density of a set of InGaAs samples grown under varying process stressed epitaxial conditions.

Abstract Evaluation techniques for semiconductor devices are keys for device development with low cost and short time to market. Especially, dopant and depletion layer distribution in devices is a critical electrical property that needs to be evaluated. Super-higher-order nonlinear dielectric microscopy (SHOSNDM) is one of the promising techniques for semiconductor device evaluation. We developed a method for imaging detailed dopant distribution and depletion layers in semiconductor devices using SHO-SNDM. As a demonstration, a cross-section of a SiC power semiconductor device was measured by this method and detailed dopant distribution and depletion layer distributions were imaged.

Abstract This paper evaluates the use of nanomilling and STEM imaging to analyze failure mechanisms in sub-50 nm InP HEMTS. The devices were life tested at elevated temperatures and biases and their electrical characteristics were measured at each stress interval. Devices that were damaged were investigated further to assess the underlying failure mechanism. Advanced microscopy with sub-nm resolution was employed to examine the physical characteristics of the failed HEMT devices at the atomic scale. As the paper explains, the examination was conducted using a focused ion beam/scanning electron microscope (FIB/SEM), an Ar gas ion nanomill, and STEM imaging.

Abstract Different epitaxial structures have been studied by high-resolution x-ray diffraction and x-ray topography, Transmission Electron Microscopy and Atomic Force Microscopy to establish correlations between epitaxial growth conditions and crystal perfection. It was confirmed that epitaxial growth under initial elastic stress inevitably leads to the creation of extended crystal defects like dislocation loops and edge dislocations in the volume of epitaxial structures, which strongly affect crystal perfection and physical properties of future devices. It was found that the type of created defects, their density and spatial distribution strongly depended on growth conditions: the value and sign of the initial elastic strain, the elastic constants of solid solutions, the temperature of deposition and growth rate, and the thickness of the epitaxial layers. All of the investigated structures were classified by their crystal perfection, using the volume density of extended defects as a parameter. It was found that the accommodation and relaxation of initial elastic stress and creation of crystal defect were up to four stages “chain” processes, necessary to stabilize the crystal structure at a level corresponding to the deterioration power of particular growth conditions.

Abstract In multilevel 3D integrated packaging, three major microstructures are viable due to the application of low volume of solders in different sizes, and/or processing conditions. Thermodynamics and kinetics of binary compounds in Cu/Sn/Cu low volume interconnection is taken into account. We show that current crowding effects can induce a driving force to cause excess vacancies saturate and ultimately cluster in the form of microvoids. A kinetic analysis is performed for electromigration mediated intermetallic growth using multiphase- field approach. Faster growth of intermetallic compounds (IMCs) in anode layer in the expense of shrinkage of cathode IMC layer in shown. This work paves the road for computationally study the ductile failure due to formation of microvoids in low volume solder interconnects in 3DICs.

Abstract Scanning microwave impedance microscopy was used to analyze a CMOS image sensor sample to reveal details of the dopant profiling in planar and cross-sectional samples. Sitespecific capacitance-voltage spectroscopy was performed on different regions of the samples.

Abstract The use of Atomic Force Microscopy (AFM) electrical measurement modes is a critical tool for the study of semiconductor devices and process development. A relatively new electrical mode, scanning microwave impedance microscopy (sMIM), measures a material’s change in permittivity and conductivity at the scale of an AFM probe tip [1]. sMIM provides the real and imaginary impedance (Re(Z) and Im(Z)) of the probe-sample interface. By measuring the reflected microwave signal as a sample of interest is imaged with an AFM, we can in parallel capture the variations in permittivity and conductivity and, for doped semiconductors, variations in the depletion-layer geometry. An existing technique for characterizing doped semiconductors, scanning capacitance microscopy, modulates the tip-sample bias and detects the tip-sample capacitance with a lock-in amplifier. A previous study compares sMIM to SCM and highlights the additional capabilities of sMIM [2], including examples of nano-scale capacitance-voltage curves. In this paper we focus on the detailed mechanisms and capabilities of the nano-scale C-V curves and the ability to extract semiconductor properties from them. This study includes analytical and finite element modeling of tip bias dependent depletion-layer geometry and impedance. These are compared to experimental results on reference samples for both doped Si and GaN doped staircases to validate the systematic response of the sMIM-C (capacitive) channel to the doping concentration.

Abstract This paper focuses on infrared (IR) thermography capabilities on III-V components for thermal measurements applications and failure analysis (FA). The first part discusses the thermal mapping on InGaAs/AlGaAs PHEMT structure and compares IR thermal measurement with the well-known techniques as Raman and SThM. The second part discusses IR thermography on challenging FA for hot spot detection on the most popular type of capacitor for III-V MMICs as the metal-insulator-metal capacitor. It shows how IR thermography can easily localize very small pinholes in SiN, where liquid crystal and OBIRCH techniques are not well adapted.

Abstract Non-stick on pad (NSOP) is a yield limiting factor that can occur due to various reasons such as particle contamination, galvanic corrosion, Fluorine-induced corrosion, process anomalies, etc. The problem of NSOP can be mitigated through a careful process characterization and optimization. In this paper, a bondpad qualification methodology (OSAT) will be discussed. It will be argued that by employing different physical analysis techniques in a failure analysis of wafer fabrication, it is possible to perform comprehensive characterization studies of the Aluminum bondpad so as to develop a robust far backend of line process. A good quality Al bondpad must meet the following four conditions-OSAT: (i) it should be no discoloration (using Optical inspection); (ii) should be defect free (using SEM inspection); (iii) should be with low contamination level (such as fluorine and carbon contamination should be within a control limit) (using Auger analysis) and (iv) should have a protective layer on bondpad surface so as to prevent bondpad corrosion (using TEM).

Abstract Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

Abstract Two-beam systems (focused ion beam (FIB) integrated with a scanning electron microscope (SEM)) have enabled site-specific analysis at the nano-scale through in situ “mill and view” capability at high resolution. In addition, a FIB-SEM can be used to cut away a lamella from a bulk sample and thin it for transmission electron microscopy (TEM) imaging. We studied the temperature dependence of FIB milling on compound semiconductors and thin films such as copper that are used in integrated circuits. These materials (GaAs, GaN, InN, etc) react chemically and physically with the gallium in the FIB and change chemical composition and may also change morphology. Copper metallization of IC’s has been difficult to mill without undesirable side effects. FIB milling for analysis of these materials becomes difficult if not impossible. Since temperature can be a big factor in chemical and physical reactions we investigated this and report here the effect of cooling the sample to cryogenic temperatures while milling. In addition, we report on the development of a process to prepare TEM lamellae with FIB entirely in a cryogenic environment.

Abstract As semiconductor devices continue to shrink, novel materials (e.g. (Si)Ge, III/V) are being tested and incorporated to boost device performance. Such materials are difficult to grow on Si wafers without forming crystalline defects due to lattice mismatch. Such defects can decrease or compromise device performance. For this reason, non-destructive, high throughput and reliable analytical techniques are required. In this paper Electron Channeling Contrast Imaging (ECCI), large area mapping and defect detection using deep learning are combined in an analytical workflow for the characterization of the defectivity of “beyond Silicon” materials. Such a workflow addresses the requirements for large areas 10 -4 cm 2 with defect density down to 10 4 cm -2 .

Abstract Scanning Capacitance Microscopy (SCM) has been extensively used for identifying doping issues in semiconductor failure analysis. In this paper, the root causes of two recent problems -- bipolar beta loss and CMOS power leakage -- were verified using SCM images. Another localization method, layer-by-layer circuit repair with IROBIRCH detection, was also utilized to locate possible defects. The resulting failure mechanism for bipolar beta loss is illustrated with a schematic cross section, which shows the leakage path from the emitter to the base. In the case of CMOS power leakage, the abnormal implantation of the Pwell region was identified with the Plane view SCM image.

Abstract Conventional FIB ex-situ lift-out is the most common technique for precise TEM sample preparation. But this method has some limitations and so in-situ lift-out technique was developed to overcome these drawbacks. The in-situ lift-out technique lifts-out the sample and then attaches the sample to a half-cut copper grid inside the FIB chamber by mini-probing system. This paper introduces a novel and simple technique that can overcome the above problems and a wide application of TEM samples preparation. The examples highlighted here demonstrate the novel method of low cost and high image quality TEM sample preparation. The method can reduce the amorphous phenomenon on the sidewall of specimen; no shield effect was found during the reprocess of thinning by ion-miller; and no contamination induced by the ion-miller sputtering was formed.

Abstract Reverse engineering (RE) is the only foolproof method of establishing trust and assurance in hardware. This is especially important in today's climate, where new threats are arising daily. A Printed Circuit Board (PCB) serves at the heart of virtually all electronic systems and, for that reason, a precious target amongst attackers. Therefore, it is increasingly necessary to validate and verify these hardware boards both accurately and efficiently. When discussing PCBs, the current state-of-the-art is non-destructive RE through X-ray Computed Tomography (CT); however, it remains a predominantly manual process. Our work in this paper aims at paving the way for future developments in the automation of PCB RE by presenting automatic detection of vias, a key component to every PCB design. We provide a via detection framework that utilizes the Hough circle transform for the initial detection, and is followed by an iterative false removal process developed specifically for detecting vias. We discuss the challenges of detecting vias, our proposed solution, and lastly, evaluate our methodology not only from an accuracy perspective but the insights gained through iteratively removing false-positive circles as well. We also compare our proposed methodology to an off-the-shelf implementation with minimal adjustments of Mask R-CNN; a fast object detection algorithm that, although is not optimized for our application, is a reasonable deep learning model to measure our work against. The Mask R-CNN we utilize is a network pretrained on MS COCO followed by fine tuning/training on prepared PCB via images. Finally, we evaluate our results on two datasets, one PCB designed in house and another commercial PCB, and achieve peak results of 0.886, 0.936, 0.973, for intersection over union (IoU), Dice Coefficient, and Structural Similarity Index. These results vastly outperform our tuned implementation of Mask R-CNN.

Abstract The continuous miniaturization trends followed by a vast majority of electronic applications results in always denser PCBs (Printed Circuit Board) designs and PCBAs (Printed Circuit Board Assembly) with increasing solder joint densities. Current high-end designs feature high layer count sequential build-up PCBs with fine lines/spaces and numerous stacked filled microvias, as well as closely spaced BGA/QFN components with pitches down to 0.4mm. In recent years, several 3D packaging approaches have emerged to further increase system integration by enabling the stacking of several dies or packages. This has translated for example into the advent of highly integrated complex System in Package (SiP) modules, Package-on-Package (PoP) assemblies or chips embedded in PCBs [1]. From a failure analysis (FA) perspective, this deep technology evolution is setting extreme challenges for accurately locating a failure site, especially when destructive techniques are not desired. The few conventional non-destructive techniques like optical or x-ray inspection are now practically becoming useless for high density PCB designs. This paper reviews several advanced analysis techniques that could be used to overcome these limitations. It will be shown through several examples how three non-destructive methods usually dedicated to package analyses can be efficiently adapted to PCBs and PCBAs: • Scanning Acoustic Microscopy (SAM) • 3D X-ray Computed Tomography (CT) • Infrared Thermography A case study of a flex-rigid board FA is presented to show the efficiency of these three techniques over classical techniques. In this example, not only the defect localization has been possible, but also the defect characterization without using destructive analysis.

Abstract III-V HBT (Heterojunction Bipolar Transistor) and HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. As well as the improvement of the MMIC performances, the localization of the defects and the failure analysis of these devices are very challenging. Active area thickness is only few nanometers, backside failure localization is mandatory because of thermal drain or metal bridge covering the front side, materials involved might be of ultimate hardness and/or high chemical sensitivity while failure mechanisms strongly differ from Si technology ones. To face these challenges, we have developed a complete approach, without degrading the component, based on backside failure analysis by electroluminescence. Its efficiency and completeness have been demonstrated through case studies.

Abstract Quantitative cathodoluminescence (CL) microscopy is a new optical spectroscopy technique that measures electron beam-induced optical emission over large field of view with a spatial resolution close to that of a scanning electron microscope (SEM). Correlation of surface morphology (SE contrast) with spectrally resolved and highly material composition sensitive CL emission opens a new pathway in non-destructive failure and defect analysis at the nanometer scale. Here we present application of a modern CL microscope in defect and homogeneity metrology, as well as failure analysis in semiconducting electronic materials.

Abstract Surface changes of copper and copper coupons coated with organic solderability preservative (OSP) after accelerated aging were measured using UV Differential Reflectance Spectroscopy. A chemometric method has been developed that allows correlation of the spectroscopic results with independent measurements of the solderability of the copper and copper/OSP coupons using a wetting balance or sequential electrochemical reduction analysis (SERA). Based on the results of this study, a versatile instrument for the assessment of the solderability of printed wiring boards has been demonstrated. The instrument is currently in beta testing at several locations.