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FinFET devices

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Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 97-101, November 6–10, 2016,
... techniques to localize the fail location within such devices in both the 22 nm and 14 nm technology nodes. 14 nm process 22 nm process electron beam absorbed current electron beam induced current failure analysis FinFET devices nanoelectronic devices sample preparation scanning electron...
Proceedings Papers

ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 451-455, November 5–9, 2017,
...Abstract Abstract This paper highlights the application of nanoprobing technique and electron tomography analysis to characterize the tiny gate oxide pinhole defect in NMOS FinFET devices. Nanoprobing technique was utilized to achieve a better understanding on the failure mechanism...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 232-237, October 28–November 1, 2018,
... microscopes gas-assisted Xe plasma FIB in-situ delayering physical failure analysis polishers probers sub-20nm FinFET devices Integration of Probing Capability into Plasma FIB for In-Situ Delayering, Defect Inspection, and EBAC on BEOL Defects of sub-20nm FinFET Devices D. Zudhistira, M.S. Wei, V...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 383-386, October 28–November 1, 2018,
...Abstract Abstract The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 305-310, November 15–19, 2020,
..., or, alternatively, eight 6144x4096 pixels, 1 s dwell time scans across the field of view of 6 m. The STI exposure experiment described above empirically illustrates the effect of subsurface ion interaction at acceleration energies of 30 kV and 5 kV, and its impact on DROs inside of modern FinFET devices. The 30...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 370-374, November 15–19, 2020,
..., and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging. chemical etching deprocessing die-level defects electrostatic discharge damage fault localization finFET devices flip-chip packaging parallel lapping solid...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 375-378, November 15–19, 2020,
...Abstract Abstract Three-dimensional device (FinFET) doping requirements are challenging due to fin sidewall doping, crystallinity control, junction profile control, and leakage control in the fin. In addition, physical failure analyses of FinFETs can frequently reach a “dead end...
Proceedings Papers

ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 388-400, November 1–5, 2015,
... milling Plasma FIB DualBeam Delayering for Atomic Force NanoProbing of 14nm FinFET Devices in an SRAM Array Roger Alvis, Trevan, Landin, Chad Rue, Peter Carleson, and Oleg Sidorov FEI Company, 5350 NE Dawson Creek Drive, Hillsboro, OR 97124, USA Presenting author e-mail: Roger.Alvis@fei.com Andrew...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 160-163, November 10–14, 2019,
... pattern generator dynamic photon emission microscopy failure analysis fin field-effect transistor infrared detectors scan tests Dynamic photon emission on FinFET devices through novel scan test approaches Ranganathan Gopinath1, Ravikumar Venkat Krishnan1,2, Lua Winson1, Phoa Angeline1, Jin Jie1 1...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 313-316, November 10–14, 2019,
... the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices. Keywords – Stacking Fault, Geometric Phase...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 329-335, November 10–14, 2019,
... memory NanoProbing on 7 nm FinFET Devices in an SRAM Array: Challenges and Solutions Anqi Qiu, William Lowe, Mridul Arora Thermofisher Scientific, Richardson, TX USA Abstract Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 372-376, November 10–14, 2019,
...Abstract Abstract This paper demonstrates a two-pin Electron Beam Induced Current (EBIC) isolation technique to isolate the defective Fin with gate oxide damage in advanced Fin Field Effect Transistor (FinFET) devices. The basic principle of this twopin configuration is similar to two-point...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 454-459, November 10–14, 2019,
... sample preparation silicon bandgap wavelength Submicron thinning of finFET devices with high power density observed in 10/7nm process nodes using high aspect ratio trenches Nathan Bakken, Vladimir Vlasyuk, Michael Beal, Ilya Artishuk Intel Corporation, Folsom, California nathan.j.bakken@intel.com...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 484-489, November 10–14, 2019,
... transition to three dimensional FinFET devices has resulted in many challenges with regard to device analysis. This is especially true when it is necessary to perform detailed dopant analysis on a specific device; the device may be comprised of a single or multiple fins that have been called out specifically...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 40-43, October 31–November 4, 2021,
...Abstract Abstract This paper presents the results of an investigation to gain a better understanding of the impact of wafer substrate copper (Cu) contamination on FinFET devices. A chip from a wafer free of Cu contamination and several chips near a Cu contaminated wafer edge were sampled...
Proceedings Papers

ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 359-361, October 31–November 4, 2021,
...Abstract Abstract This paper explains how tunneling atomic force microscopy (AFM) was used to determine the cause of leakage in FinFETs along the boundary of SRAM cells. The leaking devices were electrically isolated using photoemission microscopy, but conventional FA techniques, including SEM...
Proceedings Papers

ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 349-352, October 28–November 1, 2018,
.... electron beam induced current fault isolation FinFET gate oxide breakdown voltage MOS capacitors root cause analysis scanning electron microscopy Identification of Defective Fin by E-beam Induced Current in Advanced FinFET Device Failure Analysis Yuting Wei, Chuan Zhang, Liangshan Chen, Oh Chong...
Proceedings Papers

ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 122-128, November 15–19, 2020,
... in a design validation exercise in which we were asked to modify the drive of a multi-finger FinFET device structure to reduce its switching speed impact on a circuit. The original sized device pulled the next node in the chain too fast, resulting in a timing upset. Deleting whole structures and bridging over...
Proceedings Papers

ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 574-579, November 6–10, 2016,
...Abstract Abstract Defect localization has become more complicated in the FinFET era. As with planar devices, it is still generally possible to electrically isolate a failure down to a single transistor. However, the complexity of certain FinFET devices can lead to ambiguity as to the exact...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 141-145, November 13–17, 2011,
...Abstract Abstract For 22nm technology node and beyond, fully depleted devices such as FinFET and ETSOI are leading candidates. Certain critical dimensions of such devices are well below 10nm, and only transmission electron microscopy (TEM) has the resolution to provide measurement with sub...