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DRAM

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Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 307-311, November 3–7, 2002,
...Abstract Abstract This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 140-143, November 2–6, 2003,
...Abstract Abstract A technique is described which allows the precise measurement of the surface area of the dielectric layer of a DRAM deep trench (DT) capacitor. It uses precision FIB sectioning, and allows determination with arbitrary accuracy. It can be used for measuring random DTs...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 144-152, November 2–6, 2003,
... experience of the common memory failures of a BEST deep trench cell with an N-MOS gate used in CMOS DRAM technology. Memory cell failures are categorized into three areas for discussion – the deep trench (DT) capacitor, the transfer gate (GC), and the borderless bit-line contact (CB) between a transistor...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 185-187, November 12–16, 2006,
... analysis focused ion beam milling mechanical polishing scanning electron microscope A Novel Method to Inspect Deep Trench Capacitor Planar Profiles in DRAM J. L. Lue, A. Huang, and T. Wang ProMOS Technologies Inc.,Hsinchu Taiwan, R. O. C. Jen-lang_lue@promos.com.tw Abstract This paper presents...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 196-201, November 12–16, 2006,
...-cause failure analysis with the dynamic random access memory (DRAM) industry. In this article, several examples are reported to carry out the applications of TEM and secondary ion mass spectrometry on crystal defect analysis and electronic characteristics of advanced 512 Mb DRAMs. crystal defects...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 339-342, November 12–16, 2006,
... to the production line for process tuning and troubleshooting. 90 nm process deep trench profile inspection DRAM failure analysis polishing process monitoring A Novel Method for Deep Trench Profile Characterization and Process Monitoring in 90nm DRAM Technology Kuo-Hui Huang, Wen-Lon Gu, Ming-De Liu...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 426-430, November 12–16, 2006,
...Abstract Abstract A functional fail of a DRAM is analyzed by using an analog output of the device as an input signal of a microscope. Local heating by an IR laser changes the pass/fail behavior and thus the analog output of the DRAM. Although the observed spots do not belong to the physical...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 46-51, November 4–8, 2007,
...Abstract Abstract Nanoprobing logic based SOI embedded DRAM cells for on-processor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 115-120, November 4–8, 2007,
...Abstract Abstract It is well known that pursuing the miniaturization of devices to lower the cost and increase high-speed performance are extremely important goals for dynamic random access memory (DRAM). Therefore, electron tomography has a high potential for application to novel generation...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 252-256, November 4–8, 2007,
...Abstract Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 227-232, November 2–6, 2008,
... and impracticable measurement times for dynamic random access memories (DRAM). The new method using a high speed comparison device allows SDL image acquisition times of a few minutes and a localization of functional DRAM fails that are caused by defects in the DRAM periphery that has not been possible before...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 423-427, November 2–6, 2008,
...Abstract Abstract We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 182-184, November 13–17, 2011,
...Abstract Abstract Data retention characteristic is one of the most critical issues in low power DRAMs because it determines idle currents of self-refresh operation. Compared to normal healthy cells, a few ppm orders of cells in a tail distribution have much higher leakage currents. The origin...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 269-274, November 13–17, 2011,
... source contact that causes lower driving ability in a SA transistor issue are concluded. atomic force microscopy DRAM devices electrical signature verification failure analysis fault localization PMOS sense amplifier transistors Wei-Chih Wang, San-Lin Liew, Hua-Sheng Chen...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 403-405, November 13–17, 2011,
...Abstract Abstract The oxide-nitride-oxide (ONO) is one of the critical layers in the deep trench (DT) capacitor of the modern DRAM structure. This paper highlights a ONO inspection methodology, which used the silicon wet etching to enhance the ONO leakage point. First, a hole was milled nearby...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 465-470, November 14–18, 2004,
...Abstract Abstract This paper studies the effects of an electron beam and an ion beam in sample preparation at the borderless bit-line contact (CB) between a transistor and a bit line in a deep trench capacitor DRAM [1] using the Transmission Electron Microscope (TEM) and the Electron Energy...
Proceedings Papers

ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 558-562, November 14–18, 2004,
...Abstract Abstract Dynamic Random Access Memory (DRAM) is the one most widespread commodity product of the microelectronic industry. Although the basis structure is quite simple, an indepth electrical characterization of the single cell is mostly correlated with huge efforts in terms of test...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 186-188, November 6–10, 2005,
...Abstract Abstract A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify...
Proceedings Papers

ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 407-412, November 6–10, 2005,
...Abstract Abstract As DRAM technology extends into 12-inch diameter wafer processing, plasma-induced wafer charging is a serious problem in DRAM volume manufacture. There are currently no comprehensive reports on the potential impact of plasma damage on high density DRAM reliability...
Proceedings Papers

ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 430-433, November 10–14, 2019,
... semiconductor defects semiconductor manufacturing Statistical Failure Analysis for Non-parametric Characteristic in DRAM Myunghoon Oak, Jongbum Lee, Jungwon Bae, Kyungrak-Cho, Minju-Shin, Choongsun Park, Sunghoon Park, Hongsun Hwang, Taeyoung Oh, Jonghoon Kim, and Jungbae Lee DRAM Product Engineering Team...