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Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 109-113, November 11–15, 2001,
...Abstract Abstract Backside photoemission microscopy [1-2] was used to analyze the major yield loss of a communication product fabricated with submicron CMOS process: functional failures of phase-lock-loop (PLL). The PLL block was covered by five metal layers and three of them were bulk metals...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 237-241, November 11–15, 2001,
...Abstract Abstract In this paper a method is presented to remove the silicon substrate from the back of a CMOS chip altogether, whilst leaving gate oxide and silicide intact. This is achieved by grinding the chip until it becomes transparent and then selectively etching the remaining silicon...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 305-311, November 11–15, 2001,
...Abstract Abstract In this paper, we introduce an example of successful failure analysis using combination of several fault localization techniques on a 0.18 um CMOS device. These techniques contain both front and backside localization techniques. Front side techniques are the following...
Proceedings Papers

ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 373-377, November 11–15, 2001,
...Abstract Abstract The work presented in this paper concerns the characterization of MEMS structures, industrially manufactured using front-side bulk micromachining post-process techniques on CMOS dies. The systematic characterization of mechanical parameters, such as stiffness or mass, on a set...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 169-171, November 3–7, 2002,
...Abstract Abstract For its latest generation of high performance logic applications, Motorola employs a 0.13 µm CMOS technology with shallow trench isolation (STI). The contact dimension and spacing requirements for the dense areas of the circuitry, such as the cache, are quite aggressive. We...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 317-323, November 3–7, 2002,
...Abstract Abstract This paper is about a sample preparation technique that is based on a previous research publication1. The technique was initially used for the investigation of salicide formation for CMOS process development. The initial results were very good and proved to be helpful...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 387-390, November 3–7, 2002,
...Abstract Abstract The light emission from ever increasing OFF-state leakage currents in advanced CMOS technologies can now be reliably measured using existing photon detectors. The measurements of such an emission provide valuable information about the operation of ICs. In this paper we suggest...
Proceedings Papers

ISTFA2002, ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis, 771-775, November 3–7, 2002,
... technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 40-44, November 2–6, 2003,
... version of the one discussed in [1] demonstrating lower performance, we will show that it provides a significant reduction in acquisition time for the collection of optical waveforms, thus maintaining the usability of the PICA technique for present and future low voltage technologies. CMOS failure...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 99-104, November 2–6, 2003,
...Abstract Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside...
Proceedings Papers

ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 206-208, November 2–6, 2003,
...Abstract Abstract Random single bit failures were encountered in cache areas of Motorola’s 0.13 µm CMOS products under development. Extensive in-line probe data and end-of-line probe data in conjunction with failure analysis indicated the presence of particles at the upper surface of tungsten...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 118-124, November 12–16, 2006,
...Abstract Abstract An aggressive yield improvement program that was undertaken by the engineering teams has culminated in the works reported in this paper. The power down current (Idd_Pd) was one of the major failure modes recorded for CMOS ICs. In essence, any improvement made on the Idd_Pd...
Proceedings Papers

ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 503-511, November 12–16, 2006,
... by means of the atomic force probe after the failure has been sufficiently localized to a minimum number of transistors. atomic force probing CMOS electrical characterization scanning election microscope scanning probe microscopy transistors wafer fabrication process Atomic Force Probe...
Proceedings Papers

ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 161-164, November 4–8, 2007,
... micron node of 45nm process. 45 nm process CMOS failure analysis microprocessor debugging noise detectors optical probing solid immersion lens time resolved emission measurements Ultra Low Voltage Probing on 45 nm CMOS by Time Resolved Emission (TRE) Technology Chi-Lin (Kenny) Young, Paul...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 349-353, November 2–6, 2008,
...Abstract Abstract The reliability of a pure CMOS One-time Programmable (PCOP) Memory was investigated. The memory is programmed with and anti-fuse formed by the breakdown of the thin gate oxide. The results of reliability stress tests show that the PCOP memory is stable and reliable for normal...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 499-504, November 2–6, 2008,
... that special care is taken to prepare a well-adapted sample. 45 nm process CMOS devices failure analysis fault localization sample preparation scanning transmission electron microscopy 3D STEM Tomography Based Failure Analysis of 45 nm CMOS Devices Frederic Lorut STMicroelectronics, 850 Rue Jean...
Proceedings Papers

ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 505-509, November 2–6, 2008,
... and Scanning Spreading Resistance Microscopy (SSRM). chemical etching CMOS process doping failure analysis nanoscale secondary ion mass spectrometry scanning spreading resistance microscopy semiconductor devices transmission electron microscopy Dopant Analysis on advanced CMOS technologies...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 66-70, November 14–18, 2010,
...Abstract Abstract Threshold voltage (Vt) shift was measured, using atomic force probing (AFP) technique, in the pullup PFETs of high density SRAM bitcell arrays in 90nm CMOS bulk technology. This shift caused catastrophic yield loss. The direct measurements of dopant distribution both in plan...
Proceedings Papers

ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 243-248, November 14–18, 2010,
...Abstract Abstract Normally, ESD-type of damage will be located near the bonding pads for the input pins. However, there have been several cases where ESD-type damage has been detected on CMOS gates at internal locations on the die, two or more transistors away from any input or output pin...
Proceedings Papers

ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 212-217, November 13–17, 2011,
... CMOS IC Identification of Extension Implant Defect in Sub-Micron CMOS ICs - Analysis Technique, Model, and Solution Yuk L. Tsang 1* , Giri Nallapati 2 , Ron Skarupa 1 , and Brian Anthony 1 1 Freescale Semiconductor Inc., Austin, TX * ra0149@freescale.com 2 Now with Qualcomm, San Diego, CA Abstract...