Abstract This paper discusses the development of an automated cell layer counting process for preparing 3D NAND flash memory samples for TEM analysis. In an initial proof-of-concept, several line markings were inscribed on the test device in evenly spaced intervals in order to evaluate its helpfulness for a human operator. A more automated procedure was then developed in which cell layers were counted to a desired target layer starting from a reference layer set by the operator. At that point, the operator could begin preparing the TEM sample.

Abstract This paper evaluates the use of plasma etching for preparing TEM specimens to analyze high aspect ratio 3D NAND integrated circuits. By controlling plasma etching parameters, a relatively high material removal rate could be obtained. Moreover, through the control of etch time, the top region of the test specimens could be completely removed down through the expected number of layers, making it possible to resolve details throughout the entire sample, particularly in the middle region of the 3D NAND, using TEM cross-section analysis.

Abstract This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells. Despite the high aspect ratio of the region of interest, the method can resolve offsets down to a few nm. Such precision is critical, as the paper explains, because the radius and thus electrical characteristics of each memory cell is determined by the etching angle.

Abstract The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.

Abstract Conventional mechanical sample preparation is a difficult and uncontrolled process that does not allow targeting of a specific depth or layer. Because of the difficulties presented by mechanical sample preparation, there has been an emergence of beam-based techniques for device delayering applications. Cross-sectioning is another commonly used technique used in microelectronics industry investigations; when combined with delayering, one can gain complete knowledge about a device's faults. This paper presents a development in semiconductor device investigation using low energy, broad-beam argon ion milling. The results highlight that broad-beam Ar ion milling produces excellent surface quality, which allows high resolution scanning electron microscope observation and energy dispersive spectrometry analyses, even at low energy.

Abstract This paper presents a novel approach for detecting channel hole bending (ChB) defects in vertical NAND flash memory. Such defects are the result of etching process inconsistencies and contribute to data loss and device failure by inducing leakage current between adjacent channel holes. In order to satisfy long-term reliability requirements and volume demand, chipmakers must be able to detect these defects prior to shipping during electrical die sorting and screening procedures. The proposed method works by monitoring leakage current differences between diagonally and horizontally adjacent memory cells and is shown to be an effective screening technique.

Abstract This paper presents a method for determining positional variation and offsets in high aspect ratio etches used in the production of 3D NAND devices. The method uses a 3D fiducial as a positional reference in the field-of-view, which not only allows for high precision tracking of features through the depth of the device, but also aids in the alignment of images when performing 3D reconstructions. The workflow is based on plasma dual beam diagonal milling, which allows users to characterize structures through the device stack at a much higher throughput/slice than conventional methods, enabling enhanced process monitoring and control.

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Abstract The development of vertical 3D NAND technology over the past 5 years has been accelerated by the parallel development of metrology techniques capable of characterizing these device stacks. Current trends point toward a continuous scaling of dimensions along the z-axis, involving a critical etch step with aspect ratios of ~50:1. These high aspect ratio process steps present both fabrication and metrology challenges where the channel holes can bend, bow, and pinch off throughout the stack. Work presented herein demonstrates the capability of an automated workflow developed using the Thermo Scientific™ Helios™ G4 HXe DualBeam™ platform. The workflow iteratively exposes desired layers within the NAND stack, collects high resolution SEM images, and performs metrology to enable statistical analysis of trends as a function of depth within the stack. Results will be presented from 3 sites in an automatically delayered 72-layer 3D NAND die. Automated SEM metrology was performed every 10 layers, capturing more than 6000 devices. Over 19000 measurements were made on imaged devices yielding assessment of statistically significant trends in the planar cell area, eccentricity, and position of the bits as a function of depth.

Abstract Focused ion beam (FIB) techniques are often used when delayering semiconductor devices. However, using FIB technology for device delayering has limitations. One of these limitations prevents the exposure of a large slope area on the sample, which reveals all layers simultaneously. The delayering process is complex and requires prior process knowledge, such as cross-section architecture, composition, and layer uniformity. This paper discusses advances in semiconductor device deprocessing for product development, failure analysis, and quality control using low-energy, argon broad ion beam (BIB) milling. Ar BIB milling is a practical solution for accurate delayering of advanced microelectronic devices. Results of the spot milling of a whole 300 mm wafer experiment and top-down delayering of wafer pieces experiment show that successful device delayering can be achieved by either spot milling or layer-by-layer milling. These two strategies are easily achieved, for either small wafer pieces or full 300 mm wafer investigation.

Abstract Modern 2D and 3D X-ray technologies are among the most useful non-destructive testing methods that enable the inspection of an object's internal features without cutting or disassembling the sample. This paper discusses the basic operating principle, advantages, and disadvantages of 2D and 3D X-ray based approaches for testing and failure analysis and describes how these different methods have practical application for failure analysis and dimensional metrology. The techniques discussed are radiography, classical laminography, computed tomography, and computed laminography.